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S75PL127JBEBAWB2 Datasheet(PDF) 2 Page - SPANSION

No. de pieza S75PL127JBEBAWB2
Descripción Electrónicos  Power supply woltage of 2.7 to 3.1 volt
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S75PL127JBEBAWB2 Datasheet(HTML) 2 Page - SPANSION

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27631A5 September 28, 2004
Advance
Info rmation
S75PL127J MCPs .................................................1
General Description ...................................................1
Product Selector Guide ............................................ 5
MCP Block Diagram ................................................ 6
Connection Diagram ................................................ 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information ............................................... 9
Valid Combinations .................................................10
Data: S29GL128N ................................................................................................ 10
Data: S29GL256N ................................................................................................ 11
Data: S29GL512N ............................................................................................... 12
S29PL127J/S29PL064J/S29PL032J for MCP .....13
General Description .................................................15
Simultaneous Read/Write Operation with Zero Latency .......................15
Page Mode Features ............................................................................................15
Standard Flash Memory Features ....................................................................15
Pin Description .........................................................17
Device Bus Operations ............................................18
Table 1. PL127J Device Bus Operations ................................ 18
Requirements for Reading Array Data ......................................................... 18
Random Read (Non-Page Read) ................................................................ 18
Page Mode Read .............................................................................................. 19
Table 2. Page Select .......................................................... 19
Simultaneous Read/Write Operation ........................................................... 19
Table 3. Bank Select .......................................................... 19
Writing Commands/Command Sequences ................................................ 20
Accelerated Program Operation .............................................................. 20
Autoselect Functions .................................................................................... 20
Standby Mode .......................................................................................................20
Automatic Sleep Mode ...................................................................................... 21
RESET#: Hardware Reset Pin ......................................................................... 21
Output Disable Mode ........................................................................................ 21
Table 4. PL127J Sector Architecture ..................................... 22
Table 5. SecSiTM Sector Addresses ...................................... 27
Autoselect Mode .................................................................................................27
Table 6. Autoselect Codes (High Voltage Method) .................. 28
Table 7. PL127J Boot Sector/Sector Block Addresses for
Protection/Unprotection ..................................................... 29
Selecting a Sector Protection Mode ............................................................. 30
Table 8. Sector Protection Schemes ..................................... 30
Sector Protection ................................................... 30
Sector Protection Schemes .................................. 30
Password Sector Protection ........................................................................... 30
WP# Hardware Protection ............................................................................ 30
Selecting a Sector Protection Mode ............................................................. 30
Persistent Sector Protection ................................. 31
Persistent Protection Bit (PPB) ........................................................................31
Persistent Protection Bit Lock (PPB Lock) ..................................................31
Persistent Sector Protection Mode Locking Bit ........................................33
Password Protection Mode ................................... 33
Password and Password Mode Locking Bit ................................................34
64-bit Password ...................................................................................................34
Write Protect (WP#) ........................................................................................34
Persistent Protection Bit Lock ....................................................................35
High Voltage Sector Protection ......................................................................35
Figure 1. In-System Sector Protection/Sector
Unprotection Algorithms...................................................... 36
Temporary Sector Unprotect .........................................................................37
Figure 2. Temporary Sector Unprotect Operation.................... 37
SecSi™ (Secured Silicon) Sector Flash Memory Region ...........................37
Factory-Locked Area (64 words) ..............................................................37
Customer-Lockable Area (64 words) ......................................................38
SecSi Sector Protection Bits ........................................................................38
Figure 3. SecSi Sector Protect Verify..................................... 39
Hardware Data Protection ..............................................................................39
Low VCC Write Inhibit ................................................................................ 39
Write Pulse “Glitch” Protection ............................................................... 39
Logical Inhibit ................................................................................................... 39
Power-Up Write Inhibit ............................................................................... 39
Common Flash Memory Interface (CFI) ............ 40
Table 9. CFI Query Identification String ................................ 40
Table 10. System Interface String ........................................ 41
Table 11. Device Geometry Definition ................................... 41
Table 12. Primary Vendor-Specific Extended Query ................ 42
Command Definitions .............................................44
Reading Array Data ...........................................................................................44
Reset Command .................................................................................................44
Autoselect Command Sequence .................................................................... 45
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ................ 45
Word Program Command Sequence ........................................................... 45
Unlock Bypass Command Sequence ........................................................46
Figure 4. Program Operation ............................................... 47
Chip Erase Command Sequence ................................................................... 47
Sector Erase Command Sequence ................................................................48
Figure 5. Erase Operation ................................................... 49
Erase Suspend/Erase Resume Commands ..................................................49
Command Definitions Tables .........................................................................50
Table 13. Memory Array Command Definitions ...................... 50
Table 14. Sector Protection Command Definitions .................. 51
Write Operation Status ........................................ 52
DQ7: Data# Polling ............................................................................................ 52
Figure 6. Data# Polling Algorithm ........................................ 54
RY/BY#: Ready/Busy# ........................................................................................55
DQ6: Toggle Bit I ............................................................................................... 55
Figure 7. Toggle Bit Algorithm ............................................. 56
DQ2: Toggle Bit II .............................................................................................. 56
Reading Toggle Bits DQ6/DQ2 ..................................................................... 56
DQ5: Exceeded Timing Limits ........................................................................ 57
DQ3: Sector Erase Timer ................................................................................ 57
Table 15. Write Operation Status ......................................... 58
Absolute Maximum Ratings ...................................59
Figure 8. Maximum Overshoot Waveforms ............................ 59
Operating Ranges ................................................... 60
Industrial (I) Devices ..........................................................................................60
Wireless Devices ................................................................................................60
Supply Voltages ...................................................................................................60
DC Characteristics .................................................. 61
Table 16. CMOS Compatible ................................................ 61
AC Characteristic ....................................................62
Test Conditions ..................................................................................................62
Figure 9. Test Setups ........................................................ 62
Table 17. Test Specifications ............................................... 62
SWITCHING WAVEFORMS ......................................................................... 63
Table 18. KEY TO SWITCHING WAVEFORMS .......................... 63
Figure 10. Input Waveforms and Measurement Levels ............ 63
VCC RampRate ................................................................................................... 63
Read Operations .................................................................................................64
Table 19. Read-Only Operations .......................................... 64
Figure 11. Read Operation Timings ...................................... 64
Figure 12. Page Read Operation Timings............................... 65
Reset ....................................................................................................................... 65
Table 20. Hardware Reset (RESET#) .................................... 65
Figure 13. Reset Timings .................................................... 66
Erase/Program Operations .............................................................................. 67
Table 21. Erase and Program Operations .............................. 67
Timing Diagrams .................................................................................................68
Figure 14. Program Operation Timings ................................. 68
Figure 15. Accelerated Program Timing Diagram.................... 68
Figure 16. Chip/Sector Erase Operation Timings .................... 69
Figure 17. Back-to-back Read/Write Cycle Timings................. 69
Figure 18. Data# Polling Timings (During Embedded
Algorithms)....................................................................... 70
Figure 19. Toggle Bit Timings (During Embedded
Algorithms)....................................................................... 70
Figure 20. DQ2 vs. DQ6 ..................................................... 71


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