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TEA5764UK Datasheet(PDF) 8 Page - NXP Semiconductors |
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TEA5764UK Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 64 page  TEA5764UK_2 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 — 9 August 2005 8 of 64 Philips Semiconductors TEA5764UK FM radio + RDS The PLL is triggered by writing to any one of the bytes FRQSETMSB, FRQSETLSB, TNCTRL1, TNCTRL2, TESTBITS, TESTMODE. Accurate validation of the PLL locking on the new frequency can take 2 ms to 10 ms. When a lock is detected, bit LD is set. 8.6 Band limits The TEA5764UK can be switched either to the Japanese FM band or to the US/Europe FM band. Setting bit BLIM to logic 0 the band range is 87.5 MHz to 108 MHz; setting bit BLIM to logic 1 selects the Japanese band range of 76 MHz to 90 MHz. 8.7 RF AGC The RF AGC (or wideband AGC) prevents overloading and limits the amount of intermodulation products created by strong adjacent channels. The RF AGC is on by default and can be turned off via the I2C-bus. The TEA5764UK also has an in-band AGC to prevent overloading by the wanted channel. The in-band AGC is always turned on. 8.8 Local or long distance receive If bit LDX = 1, the LNA gain is reduced by 6 dB to prevent distortion when a transmitter is very near. If bit LDX = 0, the LNA gain is normal to receive long distance (DX) stations. 8.9 IF filter A fully integrated IF filter is built-in. 8.10 FM demodulator The FM quadrature demodulator has an integrated resonator to perform the phase shift of the IF signal. 8.11 IF counter The received signal is mixed to produce an IF of 225 kHz. The result of the mixing is counted. A good IF count result indicates that the radio is tuned to a valid channel instead of an image or a channel with much interference. The IF counter outputs a 7-bit count result via the I2C-bus. The IF counter is continuously active and can be read at any time via the I2C-bus. It also activates a flag when the IF count result is outside the IF count valid result window; see Section 9.1.4.4. Before a tuning cycle is initiated the IF count period can be set to 2 ms or to 15.6 ms by bit IFCTC. When the IF count period is set to 2 ms, initiating the tuning algorithm with a preset (bit SM = 0) will always give an RDS update as shown in Section 8.22.1. In case the IF count time is set to 15.6 ms, the tuning flowchart illustrated in Figure 3 is used. Once tuned, the IF count period is always 15.6 ms. |
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