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SMJ320VC33GNMM150 Datasheet(PDF) 3 Page - Texas Instruments |
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SMJ320VC33GNMM150 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 54 page SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002 3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 30 94 32 33 34 35 36 37 38 39 93 92 91 90 89 88 87 86 85 40 84 31 NC - No internal connection 41 83 NC NC NC A20 VSS A19 A18 A17 DVDD A16 A15 VSS A14 A13 CVDD A12 A11 DVDD A10 A9 VSS A8 A7 A6 A5 DVDD A4 VSS A3 A2 CVDD A1 A0 DVDD PAGE3 PAGE2 VSS PAGE1 PAGE0 NC NC NC NC NC DVDD CLKR FSR0 VSS DR0 TRST TMS CVDD TDI TDO TCK VSS EMU0 EMU1 DVDD D0 D1 D2 D3 VSS D4 D5 DVDD D6 D7 CVDD D8 D9 VSS D10 D11 DVDD D12 D13 D14 D15 NC NC HFG PACKAGE†‡ (TOP VIEW) † DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. ‡ PLLVDD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and VSS, respectively. The SM/SMJ320VC33 device is packaged in 164-pin low-profile quad flatpacks (HFG Suffix) and in 144-ball fine pitch ball grid arrays (GNL and GNM Suffix). |
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