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74LVC1G74GT Datasheet(PDF) 10 Page - NXP Semiconductors

No. de pieza 74LVC1G74GT
Descripción Electrónicos  Single D-type flip-flop with set and reset; positive edge trigger
Download  19 Pages
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Fabricante Electrónico  PHILIPS [NXP Semiconductors]
Página de inicio  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LVC1G74GT Datasheet(HTML) 10 Page - NXP Semiconductors

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2005 Feb 01
10
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
th
hold time D to CP
see Figs 6 and 8 1.65 to 1.95
0.0
−−
ns
2.3 to 2.7
0.3
−−
ns
2.7
0.5
−−
ns
3.0 to 3.6
1.2
0.6(2)
ns
4.5 to 5.5
0.5
−−
ns
fmax
maximum clock pulse frequency see Figs 6 and 8 1.65 to 1.95
80
−−
MHz
2.3 to 2.7
175
−−
MHz
2.7
175
−−
MHz
3.0 to 3.6
175
280(2)
MHz
4.5 to 5.5
200
−−
MHz
Tamb = −40 °C to +125 °C
tPHL/tPLH
propagation delay CP to Q, Q
see Figs 6 and 8 1.65 to 1.95
1.5
13.4
ns
2.3 to 2.7
1.0
7.1
ns
2.7
1.0
7.1
ns
3.0 to 3.6
1.0
5.9
ns
4.5 to 5.5
1.0
4.1
ns
propagation delay SD to Q, Q
see Figs 7 and 8 1.65 to 1.95
1.5
12.9
ns
2.3 to 2.7
1.0
7.0
ns
2.7
1.0
7.0
ns
3.0 to 3.6
1.0
5.9
ns
4.5 to 5.5
1.0
4.1
ns
propagation delay RD to Q, Q
see Figs 7 and 8 1.65 to 1.95
1.5
12.9
ns
2.3 to 2.7
1.0
7.0
ns
2.7
1.0
7.0
ns
3.0 to 3.6
1.0
5.9
ns
4.5 to 5.5
1.0
4.1
ns
tW
clock pulse width HIGH or LOW
see Figs 6 and 8 1.65 to 1.95
6.2
−−
ns
2.3 to 2.7
2.7
−−
ns
2.7
2.7
−−
ns
3.0 to 3.6
2.7
−−
ns
4.5 to 5.5
2.0
−−
ns
set or reset pulse width LOW
see Figs 7 and 8 1.65 to 1.95
6.2
−−
ns
2.3 to 2.7
2.7
−−
ns
2.7
2.7
−−
ns
3.0 to 3.6
2.7
−−
ns
4.5 to 5.5
2.0
−−
ns
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)


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