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TPS65020RHAT Datasheet(PDF) 11 Page - Texas Instruments |
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TPS65020RHAT Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 44 page  www.ti.com TPS65020 SLVS607 – SEPTEMBER 2005 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. Input signal indicating default VDCDC1 voltage, 0 = 3 V, 1 = 3.3 V This pin can also be connected to DEFDCDC1 10 I a resistor divider between VDCDC1 and GND. If the output voltage of the DCDC1 converter is set in a range from 0.6 V to VINDCDC1 V Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 2.5 V This pin can also be connected DEFDCDC2 32 I to a resistor divider between VDCDC2 and GND. If the output voltage of the DCDC2 converter is set in a range from 0.6 V to VINDCDC2 V Input signal indicating default VDCDC3 voltage, 0 = 1.3 V, 1 = 1.55 V This pin can also be connected DEFDCDC3 1 I to a resistor divider between VDCDC3 and GND. If the output voltage of the DCDC3 converter is set in a range from 0.6 V to VINDCDC3 V DCDC1_EN 25 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator. DCDC2_EN 24 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator. DCDC3_EN 23 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator. LDO REGULATOR SECTION VINLDO 19 I I Input voltage for LDO1 and LDO2 VLDO1 20 O Output voltage of LDO1 VLDO2 18 O Output voltage of LDO2 LDO_EN 22 I Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs VBACKUP 15 I Connect the backup battery to this input pin. VRTC 16 O Output voltage of the LDO/switch for the real time clock VSYSIN 14 I Input of system voltage for VRTC switch CONTROL AND I2C SECTION HOT_RESET 11 I Push button input used to reboot or wake-up processor via RESPWRON output pin TRESPWRON 26 I Connect the timing capacitor to this pin to set the reset delay time: 1 nF → 100 ms RESPWRON 27 O Open drain System reset output PWRFAIL 31 O Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition. LOW_BAT 21 O Open drain output of LOW_BAT comparator INT 28 O Open drain output SCLK 30 I Serial interface clock line SDAT 29 I/O Serial interface data/address PWRFAIL_SNS 38 I Input for the comparator driving the PWRFAIL output LOWBAT_SNS 39 I Input for the comparator driving the LOW_BAT output PB_IN 12 I/O Push button input debounced and output fed to latch at PB_OUT PB_OUT 13 I/O Open drain output of latch driven by PB_IN. Low after power up. 11 |
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