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GD5F1GQ4UFFIS Datasheet(PDF) 20 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD5F1GQ4UFFIS Datasheet(HTML) 20 Page - GigaDevice Semiconductor (Beijing) Inc. |
20 / 59 page SPI(x1/x2/x4) NAND Flash 1G 20 9.6 Read From Cache x4 (6BH) The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache x4 command. Figure9-5. Read From Cache x4 Sequence Diagram Command 0 1 2 3 4 5 6 7 6BH CS# SCLK SI SO High-Z 34 35 36 37 33 38 39 32 6 5 4 3 2 1 0 7 CS# SCLK Dummy Byte 15 16 17 18 19 20 21 30 31 10 11 12 13 9 14 8 6 5 4 3 2 1 0 7 Dummy Byte 42 43 44 45 41 46 47 40 WP#(SIO2) HOLD#(SIO3) SI(SIO0) SO(SIO1) 1 5 1 5 1 5 1 Byte0 5 0 4 0 4 0 4 0 4 4 5 2 6 2 6 2 6 2 6 6 3 7 3 7 3 7 3 7 7 Byte1 Byte2 Byte3 3 2 1 0 15 A15-0 14 12 11 13 |
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