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GD25B257DBIG Datasheet(PDF) 67 Page - GigaDevice Semiconductor (Beijing) Inc.

No. de pieza GD25B257DBIG
Descripción Electrónicos  3.3V Uniform Sector Dual and Quad Serial Flash
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Fabricante Electrónico  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Página de inicio  http://www.gigadevice.com/
Logo GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD25B257DBIG Datasheet(HTML) 67 Page - GigaDevice Semiconductor (Beijing) Inc.

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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B257D
67
8.36.
Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. Each security register contains
four pages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch
(WEL) bit before sending the Program Security Registers command. The Program Security Registers command is entered
by driving CS# Low, followed by the command code (42H), three address Bytes and at least one data Byte on SI. As soon
as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program
Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed.
At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program
Security Registers command will be ignored.
Table 18. Security Registers
Address
A23-16
A15-12
A11
A10-0
Security Register #1
00H
0 0 0 1
0
Byte Address
Security Register #2
00H
0 0 1 0
0
Byte Address
Security Register #3
00H
0 0 1 1
0
Byte Address
Figure 74. Program Security Registers command Sequence Diagram (ADS=0)
Figure 75.Program Security Registers command Sequence Diagram (ADS=1)
Command
0
1
2
3
4
5
6
7
42H
CS#
SCLK
SI
8
9 10
28 29 30 31
3
2
1
0
23 22 21
24-bit address
42 43 44 45
41
46 47
40
50 51 52 53
49
54 55
48
6
5
4
3
2
1
0
7
CS#
SCLK
SI
MSB
Data Byte 2
32 33 34 35
7
6
5
4
3
2
1
0
MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
Data Byte 1
Data Byte 3
Data Byte 256
MSB
MSB
MSB
36 37 38 39
Command
0
1
2
3
4
5
6
7
42H
CS#
SCLK
SI
8
9 10
36 37 38 39
3
2
1
0
31 30 29
32-bit address
58 59 60 61
57
62 63
56
6
5
4
3
2
1
0
7
CS#
SCLK
SI
MSB
Data Byte 2
7
6
5
4
3
2
1
0
MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
Data Byte 1
Data Byte 3
Data Byte 256
MSB
MSB
MSB
42 43 44 45
41
46 47
40
50 51 52 53
49
54 55
48


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