Data Sheet

TDA6170X

Semiconductor Group

5

21.7.99

7

Circuit Description

7.1

General

The sound intermediate frequencies contained in the baseband of a demodulated FM satellite signal can lie

between 5 and 9.9 MHz. This band of frequencies is applied rough filtered to the high-pass input of the con-

verter mixer. The purpose of this mixer is to convert the different sound IF‘s in the baseband to fixed output

frequencies (e.g. 10.7 / 10.72 MHz). These frequencies are then fed by external filters to the three sound IF

inputs.

The VCO of the mixer can be continuously tuned between 29 and 40 MHz in 20 kHz increments with crystal

accuracy by means of a PLL circuit.

The settings of the programmable divider and switching of the IF MUX and de-emphasis networks and volume

Pin 5 (CAS) offers two switchable chip addresses to enable parallel operation of two devices.

All pins are guarded against electrostatic discharge. SCL and SDA include special protective structures to

permit continued bus operation when the device is switched off.

7.2

PLL Description

The VCO signal is applied to the PLL input. It passes through a programmable divider (N=1024 to 2047) and

quency is derived from a 4 MHz crystal oscillator whose signal is divided by 200.

The phase detector has a charge pump push-pull current output. If the negative edge of the divided VCO sig-

nal appears before the negative edge of the reference signal, the current source I+ will pulse for the duration

of the phase difference. In the reverse case it is the current sink I-. If both signals are in phase, the output has

a high impedance and the PLL is locked. The current pulses are filtered by means of an integrator.

The pump current can be switched between two values (1 and 5) by software with a control bit 5I. This permits

a change in the control response during and after lock-in state.

7.3

Information is exchanged between the processor and the sound IF device on an fast asynchronous bidirec-

tional data bus. The timing for this comes from the processor (input SCL), while pin SDA functions as an I/O

depending on the direction of the data (open collector; external pull-up resistor). The bus will work with clock

frequencies up to 400 kHz.

to their function. When the bus is not busy, both lines are in the marking state (SDA, SCL are high). Each tel-

egram begins with the start condition: SDA goes low while SCL remains high. All further exchanges of infor-

mation occur when SCL is low and are read by the controller with the positive clock edge. If SDA goes high

gram.

For what follows, refer to the table of logic assignments below.

All telegrams are transferred byte for byte, followed by a ninth clock pulse during which the controller pulls the

SDA line to low (i.e. acknowledge condition). The first byte consists of seven address bits with which the proc-

essor selects the PLL from among several other peripheral devices (chip select). The eighth bit is always low.

The first bit of the first or third data byte in the data part of the telegram determines whether a divider ratio or

control information for the IF or audio part will follow. In every case the first byte must be followed by a byte of

the same data type (or stop condition). When the supply voltage is applied, a power-on reset circuit prevents

the PLL from pulling the SDA line to low and thus blocking the bus.