COP888CG datasheet(26/40 Pages) NSC

No. de pieza	COP888CG

Descripción Electrónicos	8-Bit One-Time Programmable (OTP) Microcontroller with 32 Kbytes of Program Memory

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Fabricante Electrónico	NSC [National Semiconductor (TI)]

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Detection of Illegal Conditions

The device can detect various illegal conditions resulting

from coding errors transient noise power supply voltage

drops runaway programs etc

Reading of undefined ROM gets zeros The opcode for soft-

ware interrupt is zero If the program fetches instructions

from undefined ROM this will force a software interrupt

thus signaling that an illegal condition has occurred

The subroutine stack grows down for each call (jump to

subroutine) interrupt or PUSH and grows up for each re-

turn or POP The stack pointer is initialized to RAM location

06F Hex during reset Consequently if there are more re-

turns than calls the stack pointer will point to addresses

070 and 071 Hex (which are undefined RAM) Undefined

RAM from addresses 070 to 07F (Segment 0) 140 to 17F

(Segment 1) and all other segments (ie Segments 3

etc) is read as all 1’s which in turn will cause the program

to return to address 7FFF Hex This is an undefined ROM

location and the instruction fetched (all 0’s) from this loca-

tion will generate a software interrupt signaling an illegal

condition

Thus the chip can detect the following illegal conditions

1 Executing from undefined ROM

2 Over ‘‘POP’’ing the stack by having more returns than

calls

When the software interrupt occurs the user can re-initialize

the stack pointer and do a recovery procedure before re-

starting (this recovery program is probably similar to that

following reset but might not contain the same program

initialization procedures) The recovery program should re-

set the software interrupt pending bit using the RPND in-

struction

MICROWIREPLUS

MICROWIREPLUS is a serial synchronous communica-

tions interface The MICROWIREPLUS capability enables

the device to interface with any of National Semiconductor’s

MICROWIRE peripherals (ie AD converters display driv-

ers E2PROMs etc) and with other microcontrollers which

support the MICROWIRE interface It consists of an 8-bit

serial shift register (SIO) with serial data input (SI) serial

data output (SO) and serial shift clock (SK)

Figure 17

shows a block diagram of the MICROWIREPLUS logic

TLDD12860 – 19

FIGURE 17 MICROWIREPLUS Block Diagram

The shift clock can be selected from either an internal

source or an external source Operating the MICROWIRE

PLUS arrangement with the internal clock source is called

the Master mode of operation Similarly operating the

MICROWIREPLUS arrangement with an external shift

clock is called the Slave mode of operation

The CNTRL register is used to configure and control the

MICROWIREPLUS mode To use the MICROWIREPLUS

the MSEL bit in the CNTRL register is set to one In the

master mode the SK clock rate is selected by the two bits

SL0 and SL1 in the CNTRL register Table VIII details the

different clock rates that may be selected

TABLE VIII MICROWIREPLUS

Master Mode Clock Select

SL1

SL0

SK

00

2 c tc

01

4 c tc

1x

8 c tc

Where tc is the instruction cycle clock

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COP888CG Datasheet(PDF) 26 Page - National Semiconductor (TI)

COP888CG Datasheet(HTML) 26 Page - National Semiconductor (TI)

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