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M390S2858DT1 Datasheet(PDF) 4 Page - Samsung semiconductor

No. de Pieza. M390S2858DT1
Descripción  128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD
Descarga  12 Pages
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Fabricante  SAMSUNG [Samsung semiconductor]
Página de inicio  http://www.samsung.com/Products/Semiconductor
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M390S2858DT1 Datasheet(HTML) 4 Page - Samsung semiconductor

 
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REV. 0.0 Jan. 2002
M390S2858DT1
PC133 Registered DIMM
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
REG
Control Signal(RAS,CAS,WE)
*1
*2
*3 DOUT
td, tr = Delay of register (74ALVCF162835)
Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register (74ALVCF162835). Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module.
: Don
′t care
*1. Register Input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
RAS
CAS
WE
RAS
CAS
WE
tSAC
tRDL
Read
Row Active
Command
Row Active
Write
Command
Precharge
Command
1CLK
td
tr
td
tr
*2. Register Output
*3. SDRAM
tRAC(refer to *1)
CAS latency(refer to *1)
=2CLK+1CLK
DQ
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Precharge
Command
CAS latency(refer to *2)
=2CLK
tRAC(refer to *2)


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