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ADSP-21366SKBCZENG Datasheet(PDF) 7 Page - Analog Devices |
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ADSP-21366SKBCZENG Datasheet(HTML) 7 Page - Analog Devices |
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7 / 54 page  ADSP-21365/6 Preliminary Technical Data Rev. PrA | Page 7 of 54 | September 2004 Left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over var- ious attributes of this mode. Each of the serial ports supports the left-justified sample pair and I2S protocols (I2S is an industry standard interface com- monly used by audio codecs, ADCs and DACs such as the Analog Devices AD183x family), with two data pins, allowing four left-justified sample pair or I2S channels (using two stereo devices) per serial port, with a maximum of up to 24 I2S chan- nels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I2S modes, data- word lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional µ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be inter- nally or externally generated. Parallel Port The Parallel Port provides interfaces to SRAM and peripheral devices. The multiplexed address and data pins (AD15–0) can access 8-bit devices with up to 24 bits of address, or 16-bit devices with up to 16 bits of address. In either mode, 8- or 16- bit, the maximum data transfer rate is 55M bytes/sec. DMA transfers are used to move data to and from internal memory. Access to the core is also facilitated through the paral- lel port register read/write functions. The RD, WR, and ALE (Address Latch Enable) pins are the control pins for the parallel port. Serial Peripheral (Compatible) Interface The ADSP-21365 SHARC processor contains two Serial Periph- eral Interface ports (SPIs). The SPI is an industry standard synchronous serial link, enabling the ADSP-21365/6 SPI com- patible port to communicate with other SPI compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, sup- porting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI compatible devices, either acting as a master or slave device. The ADSP-21365/6 SPI compatible peripheral imple- mentation also features programmable baud rate and clock phase and polarities. The ADSP-21365/6 SPI compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention. S/PDIF Compatible Digital Audio Receiver/Transmitter and Synchronous/Asynchronous Sample Rate Converter The S/PDIF transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the transmitter can be formatted as left justified, I2S or right justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF transmitter are routed through the Signal Routing Unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), or the sample rate converters (SRC) and are controlled by the SRU control registers. The sample rate converter (SRC) contains four SRC blocks and is the same core as that used in the AD1896 192 kHz Stereo Asynchronous Sample Rate Converter and provides up to 128dB SNR. The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to con- vert multichannel audio data without phase mismatches. Finally, the SRC is used to clean up audio data from jittery clock sources such as the S/PDIF receiver. Digital Transmission Content Protection The DTCP specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting and tampering as it traverses high performance digital buses, such as the IEEE 1394 standard. Only legitimate entertainment content delivered to a source device via another approved copy protection system (such as the DVD Content Scrambling System) will be protected by this copy protection system. This feature is only available on the ADSP-21365 processor. Pulse Width Modulation The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM wave- forms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in non paired mode (applicable to a single group of four PWM waveforms). The entire PWM module has four groups of four PWM outputs each. Therefore, this module generates 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs. The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the mid-point of the PWM period. In double update mode, a sec- ond updating of the PWM registers is implemented at the mid- point of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic dis- tortion in three-phase PWM inverters. |
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