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SST89E58RD2-40-C-TQI Datasheet(PDF) 14 Page - Silicon Storage Technology, Inc |
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SST89E58RD2-40-C-TQI Datasheet(HTML) 14 Page - Silicon Storage Technology, Inc |
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14 / 91 page  14 Preliminary Specifications FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2 ©2004 Silicon Storage Technology, Inc. S71255-00-000 3/04 3.2.1 Reset Configuration of Program Memory Block Switching Program memory block switching is initialized after reset according to the state of the Start-up Configuration bit SC0 and/or SC1. The SC0 and SC1 bits are programmed via an external host mode command or an IAP Mode com- mand. See Table 4-1, Table 4-6, and Table 4-7. Once out of reset, the SFCF[0] bit can be changed dynam- ically by the program for desired effects. Changing SFCF[0] will not change the SC0 bit. Caution must be taken when dynamically changing the SFCF[0] bit. Since this will cause different physical memory to be mapped to the logical program address space. The user must avoid executing block switching instructions within the address range 0000H to 1FFFH. 3.3 Data RAM Memory The data RAM has 1024 bytes of internal memory. The RAM can be addressed up to 64KB for external data memory. 3.4 Expanded Data RAM Addressing The SST89E/V554A both have the capability of 1K of RAM. See Figure 3-5. The device has four sections of internal data memory: 1. The lower 128 Bytes of RAM (00H to 7FH) are directly and indirectly addressable. 2. The higher 128 Bytes of RAM (80H to FFH) are indirectly addressable. 3. The special function registers (80H to FFH) are directly addressable only. 4. The expanded RAM of 768 Bytes (00H to 2FFH) is indirectly addressable by the move external instruction (MOVX) and clearing the EXTRAM bit. (See “Auxiliary Register (AUXR)” in Section 3.6, “Special Function Registers”) Since the upper 128 bytes occupy the same addresses as the SFRs, the RAM must be accessed indirectly. The RAM and SFRs space are physically separate even though they have the same addresses. When instructions access addresses in the upper 128 bytes (above 7FH), the MCU determines whether to access the SFRs or RAM by the type of instruction given. If it is indirect, then RAM is accessed. If it is direct, then an SFR is accessed. See the examples below. Indirect Access: MOV @R0, #data ; R0 contains 90H Register R0 points to 90H which is located in the upper address range. Data in “#data” is written to RAM location 90H rather than port 1. Direct Access: MOV 90H, #data ; write data to P1 Data in “#data” is written to port 1. Instructions that write directly to the address write to the SFRs. To access the expanded RAM, the EXTRAM bit must be cleared and MOVX instructions must be used. The extra 768 bytes of memory is physically located on the chip and logically occupies the first 768 bytes of external memory (addresses 000H to 2FFH). When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. Accessing the expanded RAM does not affect ports P0, P3.6 (WR#), P3.7 (RD#), or P2. With EXTRAM = 0, the expanded RAM can be accessed as in the following example. TABLE 3-3: SFCF VALUES UNDER DIFFERENT RESET CONDITIONS (SST89E/V5XRD2) SC11 1. P = Programmed (Bit logic state = 0), U = Unprogrammed (Bit logic state = 1) SC01 State of SFCF[1:0] after: Power-on or External Reset WDT Reset or Brown-out Reset Software Reset U (1) U (1) 00 (default) x0 10 U (1) P (0) 01 x1 11 P (0) U (1) 10 10 10 P (0) P (0) 11 11 11 T3-3.0 1255 TABLE 3-4: SFCF VALUES UNDER DIFFERENT RESET CONDITIONS (SST89E/V516RD2) SC01 1. P = Programmed (Bit logic state = 0), U = Unprogrammed (Bit logic state = 1) State of SFCF[1:0] after: Power-on or External Reset WDT Reset or Brown-out Reset Software Reset U (1) 00 (default) x0 10 P (0) 01 x1 11 T3-4.0 1255 |
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