Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
SST89V58RD2-33-C-PJ Datasheet(PDF) 63 Page - Silicon Storage Technology, Inc |
|
SST89V58RD2-33-C-PJ Datasheet(HTML) 63 Page - Silicon Storage Technology, Inc |
63 / 91 page Preliminary Specifications FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2 63 ©2004 Silicon Storage Technology, Inc. S71255-00-000 3/04 10.0 RESET A system reset initializes the MCU and begins program execution at program memory location 0000H. The reset input for the device is the RST pin. In order to reset the device, a logic level high must be applied to the RST pin for at least two machine cycles (24 clocks), after the oscillator becomes stable. ALE, PSEN# are weakly pulled high dur- ing reset. During reset, ALE and PSEN# output a high level in order to perform a proper reset. This level must not be affected by external element. A system reset will not affect the 1 KByte of on-chip RAM while the device is running, however, the contents of the on-chip RAM during power up are indeterminate. Following reset, all Special Function Registers (SFR) return to their reset values outlined in Tables 3-7 to 3-11. 10.1 Power-on Reset At initial power up, the port pins will be in a random state until the oscillator has started and the internal reset algo- rithm has weakly pulled all pins high. Powering up the device without a valid reset could cause the MCU to start executing instructions from an indeterminate location. Such undefined states may inadvertently cor- rupt the code in the flash. When power is applied to the device, the RST pin must be held high long enough for the oscillator to start up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid power-on reset. An exam- ple of a method to extend the RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10 µF capacitor and to VSS through an 8.2KΩ resistor as shown in Figure 10-1. Note that if an RC circuit is being used, provisions should be made to ensure the VDD rise time does not exceed 1 millisecond and the oscillator start- up time does not exceed 10 milliseconds. For a low frequency oscillator with slow start-up time the reset signal must be extended in order to account for the slow start-up time. This method maintains the necessary relationship between VDD and RST to avoid programming at an indeterminate location, which may cause corruption in the code of the flash. The power-on detection is designed to work as power up initially, before the voltage reaches the brown-out detection level. The POF flag in the PCON register is set to indicate an initial power up condi- tion. The POF flag will remain active until cleared by soft- ware. Please refer to Section 3.5, PCON register definition for detail information. For more information on system level design techniques, please review the Design Considerations for the SST FlashFlex51 Family Microcontroller application note. FIGURE 10-1: POWER-ON RESET CIRCUIT 10.2 Software Reset The software reset is executed by changing SFCF[1] (SWR) from “0” to “1”. A software reset will reset the pro- gram counter to address 0000H. All SFR registers will be set to their reset values, except SFCF[1] (SWR), WDTC[2] (WDTS), and RAM data will not be altered. 10.3 Brown-out Detection Reset The device includes a brown-out detection circuit to protect the system from severed supplied voltage VDD fluctuations. SST89E5xxRD2 internal brown-out detection threshold is 3.85V, SST89V5xxRD2 brown-out detection threshold is 2.35V. For brown-out voltage parameters, please refer to Tables 14-6 and 14-7. When VDD drops below this voltage threshold, the brown- out detector triggers the circuit to generate a brown-out interrupt but the CPU still runs until the supplied voltage returns to the brown-out detection voltage VBOD. The default operation for a brown-out detection is to cause a processor reset. VDD must stay below VBOD at least four oscillator clock peri- ods before the brown-out detection circuit will respond. Brown-out interrupt can be enabled by setting the EBO bit in IEA register (address E8H, bit 3). If EBO bit is set and a brown-out condition occurs, a brown-out interrupt will be generated to execute the program at location 004BH. It is required that the EBO bit be cleared by software after the brown-out interrupt is serviced. Clearing EBO bit when the brown-out condition is active will properly reset the device. If brown-out interrupt is not enabled, a brown-out condition will reset the program to resume execution at location 0000H. 1255 F30.0 VDD VDD 10µF + - 8.2K SST89E/V5xxRD2 RST XTAL2 XTAL1 C1 C2 |
Número de pieza similar - SST89V58RD2-33-C-PJ |
|
Descripción similar - SST89V58RD2-33-C-PJ |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |