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SST89V52RD2-33-I-PJ Datasheet(PDF) 58 Page - Silicon Storage Technology, Inc |
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SST89V52RD2-33-I-PJ Datasheet(HTML) 58 Page - Silicon Storage Technology, Inc |
58 / 91 page 58 Preliminary Specifications FlashFlex51 MCU SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2 SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2 ©2004 Silicon Storage Technology, Inc. S71255-00-000 3/04 8.3.4 Pulse Width Modulator The Pulse Width Modulator (PWM) mode is used to gener- ate 8-bit PWMs by comparing the low byte of the PCA timer (CL) with the low byte of the compare register (CCAPnL). When CL < CCAPnL the output is low. When CL ≥ CCAPnL the output is high. To activate this mode, the user must set the PWM and ECOM bits in the module’s CCAPMn SFR. (See Figure 8-5 and Table 8-7) In PWM mode, the frequency of the output depends on the source for the PCA timer. Since there is only one set of CH and CL registers, all modules share the PCA timer and fre- quency. Duty cycle of the output is controlled by the value loaded into the high byte (CCAPnH). Since writes to the CCAPnH register are asynchronous, a new value written to the high byte will not be shifted into CCAPnL for compari- son until the next period of the output (when CL rolls over from 255 to 00). To calculate values for CCAPnH for any duty cycle, use the following equation: CCAPnH = 256(1 - Duty Cycle) where CCAPnH is an 8-bit integer and Duty Cycle is a fraction. FIGURE 8-5: PCA PULSE WIDTH MODULATOR MODE TABLE 8-7: PULSE WIDTH MODULATOR FREQUENCIES PCA Timer Mode PWM Frequency 12 MHz 16 MHz 1/12 Oscillator Frequency 3.9 KHz 5.2 KHz 1/4 Oscillator Frequency 11.8 KHz 15.6 KHz Timer 0 Overflow: 8-bit 15.5 Hz 20.3 Hz 16-bit 0.06 Hz 0.08 Hz 8-bit Auto-Reload 3.9 KHz to 15.3 Hz 5.2 KHz to 20.3 Hz External Input (Max) 5.9 KHz 7.8 KHz T8-7.0 1255 1255 F27.0 ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn n=0 to 4 CL CCAPnL CCAPnH PCA Timer/Counter 0 00 00 8-bit Comparator Overflow CL < CCAPnL CL >= CCAPnL Enable CEXn 0 1 |
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