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MC10105FNR2 Datasheet(PDF) 1 Page - ON Semiconductor |
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MC10105FNR2 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 5 page MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3–21 REV 5 © Motorola, Inc. 1996 3/93 Triple 2-3-2-Input OR/NOR Gate The MC10105 is a triple 2–3–2 input OR/NOR gate. PD = 30 mW typ/gate (No Load) tpd = 2.0 ns typ tr, tf = 2.0 ns typ (20%–80%) LOGIC DIAGRAM VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 12 15 13 14 5 2 43 11 7 9 6 10 MC10105 DIP PIN ASSIGNMENT VCC1 AOUT AOUT AIN AIN BOUT BOUT VEE VCC2 COUT COUT CIN CIN BIN BIN BIN 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–11 of the Motorola MECL Data Book (DL122/D). L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 FN SUFFIX PLCC CASE 775–02 |
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