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MC10E142 Datasheet(PDF) 1 Page - ON Semiconductor |
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MC10E142 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 4 page D2 D3 D4 VCCO Q0 Q1 Q2 VCCO D5 D6 D7 D8 SEL MR CLK1 CLK2 VEE S-IN D0 D1 26 27 28 2 3 4 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 5 6 7 8 9 10 Q8 Q7 Q6 VCC Q5 VCCO Q4 Q3 1 LOGIC DIAGRAM S-IN D0 D1 D2 D3 D8 SEL CLK1 CLK2 MR Q0 Q1 Q2 Q3 Q8 D Q D D D D Q Q Q Q 1 0 1 0 1 0 1 0 1 0 Pinout: 28-Lead PLCC (Top View) * All VCC and VCCO pins are tied together on the die. MOTOROLA SEMICONDUCTOR TECHNICAL DATA 2–1 REV 2 © Motorola, Inc. 1996 12/93 9Bit Shift Register The MC10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 – D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated. • 700MHz Min. Shift Frequency • 9-Bit for Byte-Parity Applications • Asynchronous Master Reset • Dual Clocks • Extended 100E VEE Range of – 4.2V to – 5.46V • 75kΩ Input Pulldown Resistors The SEL (Select) input pin is used to switch between the two modes of operation — SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the resisters to zero. PIN NAMES Pin Function D0 – D8 Parallel Data Inputs S-IN Serial Data Input SEL Mode Select Input CLK1, CLK2 Clock Inputs MR Master Reset Q0 – Q8 Data Outputs FUNCTIONS SEL Mode L H Load Shift MC10E142 MC100E142 9-BIT SHIFT REGISTER FN SUFFIX PLASTIC PACKAGE CASE 776-02 |
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