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LMS7002M Datasheet(PDF) 15 Page - List of Unclassifed Manufacturers |
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LMS7002M Datasheet(HTML) 15 Page - List of Unclassifed Manufacturers |
15 / 27 page LMS7002M 15 LMS7002M – FPRF MIMO Transceiver IC SCLK Don’t care SEN SDIO Don’t care A14 1 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Write instruction Data Don’t care Don’t care tES tDS tDH tEH Figure 42: SPI write cycle, 3-wire and 4-wire modes SCLK Don’t care SEN SDIO Don’t care A14 0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Read instruction Don’t care Don’t care tES tDS tDH tEH SDO Don’t care Output Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Don’t care tOD Figure 43: SPI read cycle, 4-wire mode (default) SCLK Don’t care SEN SDIO Don’t care A14 0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Read instruction Don’t care tES tDS tDH tEH Output Data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Don’t care tOD Figure 44: SPI read cycle, 3-wire mode SPI Memory Map The LMS7002M configuration registers are divided into a number of logical blocks as shown in Table 11. Integer and fractional parts of the PLL feedback divider are stored in a number of configuration memory registers. To change their values, multiple SPI write cycles are required. Hence, the controlled PLL will continue to output at the previously selected frequency until all NINT and NFRAC registers are updated. Otherwise it would generate an unpredicted and wrong LO frequency while being configured. Such parameters are provided through shadow registers. Shadow registers are clocked by the PLL reference clock and output new values simultaneously at first positive clock edge after SEN goes high, i.e. after updating of shadowed parameters via SPI is finished. Module Description Module address [4:0] Register address space [5:0] Microcontroller (MCU) 00000 00xxxx Lime Light port 00000 1xxxxx Top Control (AFE, BIAS, XBUF, CGEN, LDO, BIST) 0001x xxxxxx TRX (TRF(A/B), TBB(A/B), RFE(A/B), RBB(A/B), SX(R/T) 0010x xxxxxx TxTSP(A/B) 01000 0xxxxx TxNCO(A/B) 01001 xxxxxx TxGFIR1(A/B) 01010 xxxxxx TxGFIR2(A/B) 01011 xxxxxx TxGFIR3a(A/B) 01100 xxxxxx TxGFIR3b(A/B) 01101 xxxxxx TxGFIR3c(A/B) 01110 xxxxxx Module Description Module address [4:0] Register address space [5:0] RxTSP(A/B) 10000 0xxxxx RxNCO(A/B) 10001 xxxxxx RxGFIR1(A/B) 10010 xxxxxx RxGFIR2(A/B) 10011 xxxxxx RxGFIR3a(A/B) 10100 xxxxxx RxGFIR3b(A/B) 10101 xxxxxx RxGFIR3c(A/B) 10110 xxxxxx Table 11: LMS7002M SPI memory map Implementing Low Voltage SPI Digital IO buffers in the SPI region are all supplied from the same pins as the digital IQ interface (pin name – DIGPRVDD2, pin ID – W33, T32, H32, AH30). All these pins must be supplied by the same supply DVDD. There is one additional supply pin (pin name – DIGPRPOC, pin ID – W31) which controls the power on circuitry of the digital pads. To implement a low voltage SPI interface, DVDD can be lowered to 1.8V. If DVDD=1.8V then all data lines in Figure 45 must also be set to 1.8V CMOS IOs for correct interface operation. The PLL reference clock input level is controlled independently of the DVDD voltage. By default it is 1.8V, but can be further lowered to 1.2V by chip controls if needed. |
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