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CAT25C65 Datasheet(Hoja de datos) 1 Page - Catalyst Semiconductor

No. de Pieza. CAT25C65
Descripción  32K/64K-Bit SPI Serial CMOS EEPROM
Descarga  11 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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CAT25C33/65
32K/64K-Bit SPI Serial CMOS EEPROM
FEATURES
s 10 MHz SPI compatible
s 1.8 to 6.0 volt operation
s Hardware and software protection
s Low power CMOS technology
s SPI modes (0,0 &1,1)
s Commercial, industrial, automotive and extended
temperature ranges
s 1,000,000 program/erase cycles
s 100 year data tetention
s Self-timed write cycle
s 8-pin DIP/SOIC and 14-pin TSSOP
s 64-byte page write buffer
s Block write protection
– Protect first page, last page, any 1/4 or lower
1/2 of EEPROM array
PIN CONFIGURATION
PIN FUNCTIONS
Pin Name
Function
SO
Serial Data Output
SCK
Serial Clock
WP
Write Protect
VCC
+1.8V to +6.0V Power Supply
VSS
Ground
CS
Chip Select
SI
Serial Data Input
HOLD
Suspends Serial Input
NC
No Connect
BLOCK DIAGRAM
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
DESCRIPTION
The CAT25C33/65 is a 32K/64K-Bit SPI Serial CMOS
EEPROM internally organized as 4Kx8/8Kx8 bits.
Catalyst’s advanced CMOS Technology substantially
reduces device power requirements. The CAT25C33/
65 features a 64-byte page write buffer. The device
operates via the SPI bus serial interface and is enabled
though a Chip Select (
CS). In addition to the Chip Select,
the clock input (SCK), data in (SI) and data out (SO) are
required to access the device. The
HOLD pin may be
used to suspend any serial communication without
resetting the serial sequence. The CAT25C32/64 is
designed with software and hardware write protection
features including Block write protection. The device is
available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and
20-pin TSSOP packages.
Doc No. 1000, Rev. F
DIP Package (P, L)
SOIC Package (S, V)
SENSE AMPS
SHIFT REGISTERS
SPI
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
I/O
CONTROL
E2PROM
ARRAY
COLUMN
DECODERS
XDEC
HIGH VOLTAGE/
TIMING CONTROL
SO
STATUS
REGISTER
BLOCK
PROTECT
LOGIC
DATA IN
STORAGE
SI
CS
WP
HOLD
SCK
SO
WP
CS
VCC
HOLD
SCK
SI
1
2
3
4
8
7
6
5
VSS
VSS
SO
WP
VCC
HOLD
SCK
SI
1
2
3
4
8
7
6
5
CS
TSSOP Package (U14, Y14)
CS
WP
HOLD
VCC
NC
NC
NC
NC
SO
NC
NC
VSS
SCK
SI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ALO
GEN FR
TM
LEAD FREE




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