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CAT25C33VI-TE13 Datasheet(PDF) 6 Page - Catalyst Semiconductor |
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CAT25C33VI-TE13 Datasheet(HTML) 6 Page - Catalyst Semiconductor |
6 / 11 page 6 CAT25C33/65 Doc. No. 1000, Rev. F Figure 2. WREN Instruction Timing Figure 3. WRDI Instruction Timing Note: Dashed Line= mode (1, 1) — — — — Note: Dashed Line= mode (1, 1) — — — — SK SI CS SO 00000 11 0 HIGH IMPEDANCE SK SI CS SO 00000 10 0 HIGH IMPEDANCE directly to Vcc or tied to Vcc through a resistor. Figure 9 illustrates hold timing sequence. STATUS REGISTER The Status Register indicates the status of the device. The RDY (Ready) bit indicates whether the CAT25C33/ 65 is busy with a write operation. When set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. This bit is read only. The WEL (Write Enable) bit indicates the status of the write enable latch . When set to 1, the device is in a Write Enable state and when set to 0 the device is in a Write Disable state. The WEL bit can only be set by the WREN instruction and can be reset by the WRDI instruction. The BP0, BP1 and BP2 (Block Protect) bits indicate which blocks are currently protected. These bits are set by the user issuing the WRSR instruction. The user is allowed to protect any quarter of the memory, the lower half of the memory, the first page or the last page by setting these bits. Once protected the user may only read from the protected portion of the array. These bits are non-volatile. The WPEN (Write Protect Enable) is an enable bit for the WP pin. The WP pin and WPEN bit in the status register control the programmable hardware write protect feature.Hardware write protection is enabled when WP is low and WPEN bit is set to high. The user cannot write to the status register (including the block protect bits and the WPEN bit) and the block protected sections in thememory array when the chip is hardware write protected. Only the sections of the memory array that are not block protected can be written. Hardware write protection is disabled when either WP pin is high or the WPEN bit is zero. DEVICE OPERATION Write Enable and Disable The CAT25C33/65 contains a write enable latch. This latch must be set before any write operation. The device powers |
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Descripción similar - CAT25C33VI-TE13 |
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