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CAT24AC128U14-1.8TE13 Datasheet(PDF) 3 Page - Catalyst Semiconductor |
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CAT24AC128U14-1.8TE13 Datasheet(HTML) 3 Page - Catalyst Semiconductor |
3 / 11 page CAT24AC128 3 Doc. No. 1028, Rev. I Power-Up Timing (1)(2) Symbol Parameter Min Typ Max Units tPUR Power-Up to Read Operation 1 ms tPUW Power-Up to Write Operation 1 ms The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. FUNCTIONAL DESCRIPTION The CAT24AC128 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24AC128 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. A.C. CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified Output Load is 1 TTL Gate and 100pF Read & Write Cycle Limits Symbol Parameter VCC = 1.8 V - 5.5 V VCC = 2.5 V - 5.5 V Min Max Min Max Units FSCL Clock Frequency 100 400 kHz tAA SCL Low to SDA Data Out 0.1 3.5 0.05 0.9 µs and ACK Out tBUF(1) Time the Bus Must be Free Before 4.7 1.2 µs a New Transmission Can Start tHD:STA Start Condition Hold Time 4.0 0.6 µs tLOW Clock Low Period 4.7 1.2 µs tHIGH Clock High Period 4.0 0.6 µs tSU:STA Start Condition Setup Time 4.0 0.6 µs (for a Repeated Start Condition) tHD:DAT Data In Hold Time 0 0 ns tSU:DAT Data In Setup Time 100 100 ns tR(1) SDA and SCL Rise Time 1.0 0.3 µs tF(1) SDA and SCL Fall Time 300 300 ns tSU:STO Stop Condition Setup Time 4.7 0.6 µs tDH Data Out Hold Time 100 50 ns tWR Write Cycle Time 5 5 ms tSP Input Suppression (SDA, SCL) 100 100 ns |
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