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CAT5419 Datasheet(PDF) 1 Page - Catalyst Semiconductor

No. de pieza CAT5419
Descripción Electrónicos  Dual Digitally Programmable Potentiometers (DPP) with 64 Taps and 2-wire Interface
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Fabricante Electrónico  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT5419 Datasheet(HTML) 1 Page - Catalyst Semiconductor

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1
DESCRIPTION
The CAT5419 is two Digitally Programmable
Potentiometers (DPP™) integrated with control logic
and 16 bytes of NVRAM memory.
A separate 6-bit control register (WCR) independently
controls the wiper tap position for each DPP. Associated
with each wiper control register are four 6-bit non-
volatile memory data registers (DR) used for storing up
to four wiper settings. Writing to the wiper control register
or any of the non-volatile data registers is via a 2-wire
serial bus (I2C-like). On power-up, the contents of the
CAT5419
Dual Digitally Programmable Potentiometers (DPP™) with
64 Taps and 2-wire Interface
FEATURES
s Two linear-taper digital potentiometers
s 64 resistor taps per potentiometer
s End-to-end resistance 2.5k
, 10k, 50kor 100k
s Potentiometer control and memory access via
2-wire interface (I2C like)
s Low wiper resistance, typically 80
s Four non-volatile wiper settings for each
potentiometer
s Recall of wiper settings at power up
s 2.5 to 6.0 volt operation
s Standby current less than 1
µA
s 1,000,000 nonvolatile WRITE cycles
s 100 year nonvolatile memory data retention
s 24-lead SOIC, 24-lead TSSOP and BGA
s Write protection for data register
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Document No. 2115, Rev. F
first data register (DR0) for each of the two potentiometers
is automatically loaded into its respective wiper control
registers (WCR).
The Write Protection (
WP) pin protects against
inadvertent programming of the data register.
The CAT5419 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
BGA
Top View - Bump Side Down
W1
W0
H0
H1
R
R
L0
L1
R
R
WIPER
CONTROL
REGISTERS
NONVOLATILE
DATA
REGISTERS
2-WIRE BUS
INTERFACE
CONTROL
LOGIC
SCL
SDA
WP
A0
A1
A2
A3
R
R
ALO
GEN FR
TM
LEAD FREE
1
2
3
4
A
B
C
D
E
F
RW0
A2
A1
RL1
RL0
WP
SDA
RW1
VCC
RH0
RH1
VSS
NC
NC
NC
NC
NC
NC
A3
NC
NC
A0
SCL
NC
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
CAT
5419
VCC
RL0
RH0
RW0
A2
WP
SDA
A1
RL1
RH1
RW1
GND
NC
NC
NC
NC
A0
NC
A3
SCL
NC
NC
NC
NC
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
CAT
5419
SDA
A1
RL1
RH1
RW1
GND
NC
NC
NC
NC
SCL
A3
WP
A2
RW0
RH0
RL0
VCC
NC
NC
NC
NC
A0
NC
SOIC Package (J, W)
TSSOP Package (U, Y)


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