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MC68HC05J1A Datasheet(PDF) 43 Page - Freescale Semiconductor, Inc |
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MC68HC05J1A Datasheet(HTML) 43 Page - Freescale Semiconductor, Inc |
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43 / 128 page  Interrupts Interrupt Sources MC68HC05J1A — Rev. 3.0 Technical Data MOTOROLA Interrupts 43 Figure 4-1. External Interrupt Logic External interrupt triggering sensitivity is a mask option. The IRQ pin can be negative edge-triggered only or negative edge- and low level-triggered. With the mask option for an edge- and level-sensitive external interrupt trigger, a falling edge or a low level on the IRQ pin latches an external interrupt request. Edge- and level-sensitive triggering allows the use of multiple wired-OR external interrupt sources. An external interrupt request is latched as long as any source is holding the IRQ pin low. With the mask option for an edge-sensitive only external interrupt trigger, a falling edge on the IRQ pin latches an external interrupt request. A subsequent external interrupt request can be latched only after the voltage level on the IRQ pin returns to logic 1 and then falls again to logic 0. LEVEL-SENSITIVE TRIGGER PA3 PA2 PA1 IRQ PA0 IRQ LATCH VDD (MASK OPTION) RST IRQ VECTOR FETCH IRQ STATUS AND CONTROL REGISTER EXTERNAL INTERRUPT REQUEST PORT A EXTERNAL INTERRUPTS ENABLED (MASK OPTION) INTERNAL DATA BUS TO BIH & BIL INSTRUCTION PROCESSING R Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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