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MC68HC05J1ACP Datasheet(PDF) 65 Page - Freescale Semiconductor, Inc |
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MC68HC05J1ACP Datasheet(HTML) 65 Page - Freescale Semiconductor, Inc |
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65 / 128 page  Parallel Input/Output (I/O) Port A MC68HC05J1A — Rev. 3.0 Technical Data MOTOROLA Parallel Input/Output (I/O) 65 7.4.4 Port A External Interrupts If the port A external interrupt mask option is selected, the PA3–PA0 pins serve as external interrupt pins in addition to the IRQ pin. External interrupt triggering sensitivity is a mask option. The PA3–PA0 pins can be positive edge-triggered or positive edge- and high level-triggered. NOTE: When testing for external interrupts, the BIH and BIL instructions test the voltage on the IRQ pin, not the state of the internal IRQ signal. Therefore, BIH and BIL cannot test the port A external interrupt pins. Figure 7-4 shows the port A I/O logic. Figure 7-4. Port A I/O Circuit PAx EXTERNAL INTERRUPT REQUEST DATA DIRECTION REGISTER A BIT DDRAx PORT A DATA REGISTER BIT PAx PULLDOWN REGISTER A BIT PDIAx READ $0004 WRITE $0004 WRITE $0000 READ $0000 WRITE $0010 100- µA PULLDOWN DEVICE PULLDOWN DEVICES ENABLED (MASK OPTION) RESET 8-mA SINK CAPABILITY (PINS PA7–PA4) (PINS PA3–PA0) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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