KMM5364003CSW datasheet(7/20 Pages) SAMSUNG

No. de pieza	KMM5364003CSW

Descripción Electrónicos	4M x 36 DRAM SIMM Using 4Mx16 & Quad CAS 4Mx4, 4K Refresh, 5V

Download	20 Pages

Scroll/Zoom	100%

Fabricante Electrónico	SAMSUNG [Samsung semiconductor]

Página de inicio	http://www.samsung.com/Products/Semiconductor

Logo

7 / 20 page

DRAM MODULE

KMM5364003CSW/CSWG

NOTES

An initial pause of 200us is required after power-up followed

by any 8 RAS-only or CAS-before-RAS refresh cycles before

proper device operation is achieved.

Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are ref-

erence levels for measuring timing of input signals. Transition

times are measured between VIH(min) and VIL(max) and are

assumed to be 5ns for all inputs.

Measured with a load equivalent to 2 TTL loads and 100pF.

Operation within the

tRCD(max) limit insures that tRAC(max)

can be met.

tRCD(max) is specified as a reference point only.

If

tRCD is greater than the specified tRCD(max) limit, then

access time is controlled exclusively by

tCAC.

Assumes that

tRCD

≥tRCD(max).

This parameter defines the time at which the output achieves

the open circuit condition and is not referenced to VOH or

VOL.

tWCS is non-restrictive operating parameter. It is included in

the

data

sheet

as

electrical

characteristics

only.

If

tWCS

≥tWCS(min), the cycle is an early write cycle and the

data out pin will remain high impedance for the duration of

the cycle.

Either

tRCH or tRRH must be satisfied for a read cycle.

These parameters are referenced to the CAS leading edge in

early write cycles.

Operation within the

tRAD(max) limit insures that tRAC(max)

can be met.

tRAD(max) is specified as reference point only. If

tRAD is greater than the specified tRAD(max) limit, then

access time is controlled by

tAA.

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

Test condition : Vih/Vil=2.6/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF

Parameter

Symbol

-5

-6

Unit

Note

Min

Max

Min

Max

Fast page mode cycle time

tPC

35

40

ns

CAS precharge time(Fast page cycle)

tCP

10

ns

RAS pulse width(Fast page cycle)

tRASP

50

200K

60

200K

ns

W to RAS precharge time(C-B-R refresh)

tWRP

10

ns

W to RAS hold time(C-B-R refresh)

tWRH

10

ns

AC CHARACTERISTICS (0

°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)

Número de pieza similar - KMM5364003CSW

Fabricante Electrónico	No. de pieza	Datasheet	Descripción Electrónicos
Samsung semiconductor	KMM5364003CK	286Kb / 17P	4M x 36 DRAM SIMM using 4Mx4 and 16M Quad CAS, 4K/2K Refresh, 5V
Samsung semiconductor	KMM5364003CKG	286Kb / 17P	4M x 36 DRAM SIMM using 4Mx4 and 16M Quad CAS, 4K/2K Refresh, 5V

More results

Descripción similar - KMM5364003CSW

Fabricante Electrónico	No. de pieza	Datasheet	Descripción Electrónicos
Samsung semiconductor	KMM5364005BSW	393Kb / 19P	4M x 36 DRAM SIMM Using 4Mx16 & Quad CAS 4Mx4, 4K Refresh, 5V
	KMM5364003BSW	351Kb / 18P	4M x 36 DRAM SIMM Using 4Mx16 & Quad CAS 4Mx4, 4K Refresh, 5V
	KMM5364005CSW	415Kb / 21P	4M x 36 DRAM SIMM Using 4Mx16 & Quad CAS 4Mx4, 4K Refresh, 5V
	KMM5368003BSW	365Kb / 18P	8M x 36 DRAM SIMM Using 4Mx16 & Quad CAS 4Mx4, 4K Refresh, 5V
	KMM5364005CK	277Kb / 15P	4M x 36 DRAM SIMM using 4Mx4 and 16M Quad CAS, 4K/2K, Refresh, 5V
	KMM5364003CK	286Kb / 17P	4M x 36 DRAM SIMM using 4Mx4 and 16M Quad CAS, 4K/2K Refresh, 5V
	KMM5324004BSW	401Kb / 19P	4M x 32 DRAM SIMM Using 4Mx16, 4K Refresh, 5V
	KMM5324000BSW	357Kb / 18P	4M x 32 DRAM SIMM Using 4Mx16, 4K Refresh, 5V
	KMM5324004CSW	435Kb / 21P	4M x 32 DRAM SIMM Using 4Mx16, 4K Refresh, 5V
	KMM5324004CK	276Kb / 15P	4M x 32 DRAM SIMM using 4Mx4, 4K/2K Refresh, 5V

More results

KMM5364003CSW Datasheet(PDF) 7 Page - Samsung semiconductor

KMM5364003CSW Datasheet(HTML) 7 Page - Samsung semiconductor

Número de pieza similar - KMM5364003CSW

Descripción similar - KMM5364003CSW

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Descarga

Enlace URL