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DAC11001A Datasheet(PDF) 18 Page - Texas Instruments

No. de Pieza. DAC11001A
Descripción  DACx1001 20-Bit, 18-Bit, and 16-Bit, Low-Noise, Ultra-Low Harmonic Distortion, Fast-Settling, High-Voltage Output, Digital-to-Analog Converters (DACs)
Descarga  42 Pages
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Fabricante  TI1 [Texas Instruments]
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DAC11001A Datasheet(HTML) 18 Page - Texas Instruments

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DAC11001A, DAC91001, DAC81001
Product Folder Links: DAC11001A DAC91001 DAC81001
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Copyright © 2019, Texas Instruments Incorporated
For the IOVDD supply, no internal POR occurs for nominal supply operation from 1.8 V (supply minimum) to 5.5 V
(supply maximum). For IOVDD supply voltages between 1.5 V (undefined operation threshold) and 0.8 V (POR
threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For an IOVDD
supply less than 0.8 V (POR threshold), the internal POR resets as long as the supply voltage is less than 0.8 V
for approximately 1 ms.
In case the DVDD, AVDD, IOVDD, VCC, or VSS supply drops to a level where the internal POR signal is
indeterminate, power cycle the device followed using a software reset.
8.3.5 Temperature Drift and Calibration
The DACx1001 includes a calibration circuit that significantly reduces the temperature drift on integrated and
differential nonlinearities. By default, this feature is disabled. Enable the temperature calibration feature by writing
1 to the EN_TMP_CAL bit (address 02h, B23). After the EN_TMP_CAL bit is set, issue a calibration cycle by
writing 1 to RCLTMP (address 04h, B8). At this point, the device enters a calibration cycle. Do not issue any
DAC update command during this period. The device has the capability to indicate the end of calibration using
two methods:
1. Read the status bit ALM (address 05h, B12) using SPI.
2. Issue an alarm on the ALARM pin by setting logic 0. To enable this feature, write 1 to ENALMP bit (address
02h, B12).
After the calibration cycle completes, update the DAC code to observe the impact at the DAC output. If the
environmental temperature changes after calibration, then recalibrate the device.
8.3.6 DAC Output Deglitch Circuit
The DACx1001 include a deglitch (track-and-hold) circuit at the output. This circuit is enabled by default. The
deglitch circuit minimizes the code-to-code glitch at the DAC output at the expense of the DAC update rate. This
circuit is disabled by writing 1 to DIS_TNH (bit 7, address 06h). Disable this circuit to enable faster update of the
DAC output, but with higher code-to-code glitches.
8.4 Device Functional Modes
8.4.1 Fast-Settling Mode and THD
The DACx1001 R2R ladder and deglitch circuit reduce the harmonic distortion for waveform generation
applications. The fast settling bit (FSET, bit 10, address 02h) is set to 1 by default, so that the DAC is configured
for enhanced THD performance. The FSET bit can be reset to 0 using an SPI write to enable fast-settling mode.
In this mode, the DAC deglitcher circuit can be configured using TNH_MASK (bits 19:18, address 02h). These
bits disable the deglitch circuit for code changes specified in Table 7. These bits are only writable when FSET =
0 (fast settling enabled) and DIS_TNH = 0 (deglitch circuit enabled).
8.4.2 DAC Update Rate Mode
The DACx1001 maximum update rate can be configured up to 1 MHz by using UP_RATE (bits 6:4, address
06h). These bits change the hold timing of the deglitch circuit. The bits are set to a 0.5-MHz DAC update rate by
default for enhanced THD performance. Changing the maximum update rate of the DAC impacts THD

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