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DAC11001A Datasheet(PDF) 20 Page - Texas Instruments

No. de Pieza. DAC11001A
Descripción  DACx1001 20-Bit, 18-Bit, and 16-Bit, Low-Noise, Ultra-Low Harmonic Distortion, Fast-Settling, High-Voltage Output, Digital-to-Analog Converters (DACs)
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Fabricante  TI1 [Texas Instruments]
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DAC11001A Datasheet(HTML) 20 Page - Texas Instruments

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DAC11001A, DAC91001, DAC81001
Product Folder Links: DAC11001A DAC91001 DAC81001
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Copyright © 2019, Texas Instruments Incorporated
Programming (continued)
As a result, the total number of clock cycles must be equal to 32 × N, where N is the total number of devices in
the daisy-chain. When the serial transfer to all devices is complete the SYNC signal is taken high. This action
transfers the data from the SPI shift registers to the internal register of each device in the daisy-chain and
prevents any further data from being clocked into the input shift register. The DACx1001 implement a bit that
enables higher speeds for clocking out data from the SDO pin. Enable this feature by setting FSDO (bit 13,
address 02h) to 1. See Timing Requirements: Read and Daisy-Chain Write, 2.7 V
≤ DVDD < 4.5 V and for more
8.5.2 CLR Pin Functionality and Software Clear
The CLR pin is an asynchronous input pin to the DAC. When activated, this level-sensitive pin clears the DAC
buffers and DAC latches to the DAC-CLEAR-DATA bits (address 03h). The device exits clear mode on the
SYNC rising edge of the next valid write to the device. If the CLR pin receives a logic 0 during a write sequence
during normal operation, the clear mode is activated and the buffer and DAC registers are immediately cleared.
The DAC registers can also be cleared using the SCLR bit (address 04h, B5); the contents are cleared at the
rising edge of SYNC.
8.5.3 Output Update (Synchronous and Asynchronous)
The DACx1004 devices offer both a software and hardware simultaneous update and control function. The DAC
double-buffered architecture has been designed so that new data can be entered for the DAC without disturbing
the analog output. Data updates can be performed either in synchronous or in asynchronous mode, depending
on the status of LDAC-MODE bit (address 02h, B14). Synchronous Update
In synchronous mode (LDACMODE = 1), the LDAC pin is used as an active-low signal for simultaneous DAC
updates. Data buffers must be loaded with the desired data before an LDAC low pulse. After an LDAC low pulse,
the DAC is updated with the last contents of the corresponding data buffers. If the content of a data buffer is not
changed, the DAC output remains unchanged after the LDAC pin is pulsed low. Asynchronous Update
In asynchronous mode (LDACMODE = 0), data are updated with the rising edge of the SYNC (when daisy-chain
mode is enabled, DSDO = 0), or at the 32nd falling edge of SCLK (When daisy-chain mode is disabled, DSDO =
1). For asynchronous updates, the LDAC pin is not required, and it must be connected to 0 V permanently.
8.5.4 Software Reset Mode
The DACx1001 implements a software reset feature. The software reset function uses the SRST bit (address
04h, B6). When this bit is set to 1, the device resets to the default state.

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