Motor de Búsqueda de Datasheet de Componentes Electrónicos
Selected language     Spanish  ▼

Delete All
ON OFF
ALLDATASHEET.ES

X  

Preview PDF Download HTML

DAC11001A Datasheet(PDF) 24 Page - Texas Instruments

No. de Pieza. DAC11001A
Descripción  DACx1001 20-Bit, 18-Bit, and 16-Bit, Low-Noise, Ultra-Low Harmonic Distortion, Fast-Settling, High-Voltage Output, Digital-to-Analog Converters (DACs)
Descarga  42 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo 

DAC11001A Datasheet(HTML) 24 Page - Texas Instruments

Zoom Inzoom in Zoom Outzoom out
 24 / 42 page
background image
24
DAC11001A, DAC91001, DAC81001
SLASEL0 – OCTOBER 2019
www.ti.com
Product Folder Links: DAC11001A DAC91001 DAC81001
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
8.6.4 DAC-CLEAR-DATA Register (address = 03h) [reset = 800000h]
Figure 11. DAC-CLEAR-DATA Register Format
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Read/
Write
Address
DAC-CLEAR-DATA (8 bits, left justified)
R/W
W
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
000h
0h
W
W
Table 8. DAC-CLEAR-DATA Register Field Descriptions
Bit
Field
Type
Reset
Description
31
Read/Write
R/W
N/A
Read when set to 1 or write when set to 0
30:24
Address
W
N/A
03h
23:16
DAC-CLEAR-DATA
R/W
80h
Stores the 8-bit data to be loaded to DAC in left-justified,
straight-binary format. DAC data registers updated with this
value when CLR pin asserted low
15:0
000h
W
N/A
N/A
8.6.5 TRIGGER Register (address = 04h) [reset = 000000h]
Figure 12. TRIGGER Register Format
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Read/
Write
Address
00h
R/W/
W
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
00h
RCLTMP
0h
SRST
SCLR
0h
0h
W
R/W
W
R/W
R/W
W
W
Table 9. TRIGGER Register Field Descriptions
Bit
Field
Type
Reset
Description
31
Read/Write
R/W
N/A
Read when set to 1 or write when set to 0
30:24
Address
W
N/A
04h
23:9
0000h
W
N/A
Unused
8
RCLTMP
R/W
0h
Trigger temperature recalibration DAC Codes
0 : No temperature recalibration (default)
1 : DAC codes recalibrated, ALARM pin is pulled low (if
ENALMP = 1) and ALM bit (Address 05) is set 1 upon calibration
completion. Subsequent DAC codes will use latest calibrated
coefficients.
7
0h
W
N/A
NA
6
SRST
R/W
0h
Software reset
0 : No software reset (default)
1 : Software reset initiated, device in default state
5
SCLR
R/W
0h
Software clear
0 : No software clear (default)
1 : Software clear initiated, DAC registers in clear mode, DAC
code set by clear select register (address 03h). DAC output
clears on 32nd SCLK falling (DSDO = 1) or SYNC rising edge
(DSDO = 0)
4
0h
W
N/A
N/A
3:0
0h
W
N/A
N/A


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42 


Datasheet Download




Enlace URL




Privacy Policy
ALLDATASHEET.ES
Does ALLDATASHEET help your business so far?  [ DONATE ]  

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Favorito   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn