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DAC11001A Datasheet(PDF) 25 Page - Texas Instruments

No. de Pieza. DAC11001A
Descripción  DACx1001 20-Bit, 18-Bit, and 16-Bit, Low-Noise, Ultra-Low Harmonic Distortion, Fast-Settling, High-Voltage Output, Digital-to-Analog Converters (DACs)
Descarga  42 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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DAC11001A Datasheet(HTML) 25 Page - Texas Instruments

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DAC11001A, DAC91001, DAC81001
www.ti.com
SLASEL0 – OCTOBER 2019
Product Folder Links: DAC11001A DAC91001 DAC81001
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
8.6.6 STATUS Register (address = 05h) [reset = 000000h]
Figure 13. STATUS Register Format
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Read/
Write
Address
00h
R
W
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0h
ALM
00h
0h
W
R
W
W
Table 10. STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
31
Read/Write
R
N/A
Read when set to 1 , read only
30:24
Address
W
N/A
05h
23:12
000h
W
N/A
N/A
11
ALM
R
0
Alarm indicator bit, This bit is not masked by ENALMP bit
0 :Temperature recalibration in progress
1 : DAC codes recalibrated, ALARM pin is pulled low (if
ENALMP = 1) Subsequent DAC codes will use latest calibrated
coefficients. Reading back this register resets ALARM pin to 1
status.
10:4
00h
W
N/A
N/A
3:0
0h
W
N/A
N/A
8.6.7 CONFIG2 Register (address = 06h) [reset = 000060h]
Figure 14. CONFIG2 Register Format
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Read/
Write
Address
00h
R/W
W
W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
00h
DIS_TNH
UP_RATE
0h
W
R/W
R/W
W
Table 11. CONFIG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
Read/Write
R/W
N/A
Read when set to 1 or write when set to 0
30:24
Address
W
N/A
06h
23:8
0000h
W
N/A
N/A
7
DIS_TNH
R/W
0h
Disable track and hold:
0 : Track and hold enabled (default)
1 : Track and hold disabled
6-4
UP_RATE
R/W
6h
DAC output max update rate:
000: 1 MHz with 38-MHz SCLK
001: 0.9 MHz with 34-MHz SCLK
010: 0.8 MHz with 31-MHz SCLK
011: 1.2 MHz with 45-MHz SCLK
100: 0.5 MHz with 21-MHz SCLK, (default)
101: 0.45 MHz with 18-MHz SCLK
110: 0.4 MHz with 16-MHz SCLK
111: 0.6 MHz with 24-MHz SCLK
3:0
0h
W
N/A
N/A


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