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DAC11001A Datasheet(PDF) 4 Page - Texas Instruments

No. de Pieza. DAC11001A
Descripción  DACx1001 20-Bit, 18-Bit, and 16-Bit, Low-Noise, Ultra-Low Harmonic Distortion, Fast-Settling, High-Voltage Output, Digital-to-Analog Converters (DACs)
Descarga  42 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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DAC11001A Datasheet(HTML) 4 Page - Texas Instruments

 
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DAC11001A, DAC91001, DAC81001
SLASEL0 – OCTOBER 2019
www.ti.com
Product Folder Links: DAC11001A DAC91001 DAC81001
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
AGND
2, 35, 38,
40, 42, 43,
46, 47
Analog
ground
Connect to 0 V.
AGND-OUT
8
Analog
ground
Connect to 0 V. Measure DAC output voltage with respect to this node.
AGND-TnH
14
Analog
ground
Connect to 0 V. Integrated deglitcher clock ground..
ALARM
19
Output
Alarm output
AVDD
39, 41
Power
Positive low voltage analog power supply
CLR
30
Input
DAC registers clear pin, active low
DGND
16, 17, 20,
21, 22, 23,
26
Digital
ground
Connect to 0 V.
DVDD
27
Power
Digital power supply pin
RFB
9
Input
Integrated precision resistor feedback node
IOVDD
28
Power
Interface power supply pin
LDAC
18
Input
Load DAC pin, active low
NC
1, 12, 13,
15, 24, 25,
29, 36, 37,
48
No connection, leave floating
OUT
7
Output
Unbuffered voltage output
RCM
11
Input
Integrated precision resistor common-mode node
REFNF
5
Input
External negative reference input. Connect to 0 V for unipolar DAC output.
REFNS
6
Input
External negative reference sense node
REFPF
3
Input
External positive reference input
REFPS
4
Input
External positive reference sense node
ROFS
10
Input
Integrated precision resistor offset node
SCLK
31
Input
Serial clock input of serial peripheral interface (SPI). Schmitt-trigger logic input.
Data are transferred at rates of up to 50 MHz.
SDIN
32
Input
Serial data input. Schmitt-trigger logic input.
Data are clocked into the input shift register on the falling edge of the serial clock input.
SDO
34
Output
Serial data output. Data are valid on the falling edge of SCLK.
SYNC
33
Input
SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless
SYNC is low. When SYNC is high, the SDO pin is in high-impedance status.
VCC
45
Power
Analog positive power supply
VSS
44
Power
Analog negative power supply


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