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DAC53401 Datasheet(PDF) 12 Page - Texas Instruments

No. de Pieza. DAC53401
Descripción  DACx3401 10-Bit and 8-Bit, Voltage-Output Digital-to-Analog Converters With Nonvolatile Memory and PMBus™ Compatible I2C Interface in Tiny 2 × 2 WSON
Descarga  43 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

DAC53401 Datasheet(HTML) 12 Page - Texas Instruments

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DAC53401, DAC43401
SLASES7 – JULY 2019
www.ti.com
Product Folder Links: DAC53401 DAC43401
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Copyright © 2019, Texas Instruments Incorporated
8.3.3.1 NVM Cyclic Redundancy Check
The DACx3401 implement a cyclic redundancy check (CRC) feature for the device NVM to make sure that the
data stored in the device NVM is uncorrupted. There are two types of CRC alarm bits implemented in
DACx3401: NVM_CRC_ALARM_USER and NVM_CRC_ALARM_INTERNAL. The NVM_CRC_ALARM_USER
bit indicates the status of user-programmable NVM bits, and the NVM_CRC_ALARM_INTERNAL bit indicates
the status of internal NVM bits The CRC feature is implemented by storing a 10-Bit CRC (CRC-10-ATM) along
with the NVM data each time NVM program operation (write or reload) is performed and during the device start
up. The device reads the NVM data and validates the data with the stored CRC. The CRC alarm bits
(NVM_CRC_ALARM_USER and NVM_CRC_ALARM_INTERNAL address D0h) report any errors after the data
are read from the device NVM.
8.3.3.2 NVM_CRC_ALARM_USER Bit
A logic 1 on NVM_CRC_ALARM_USER bit indicates that the user-programmable NVM data is corrupt. During
this condition, all registers in the DAC are initialized with factory reset values, and any DAC registers can be
written to or read from. To reset the alarm bits to 0, issue a software reset (see the Software Reset section)
command, or cycle power to the DAC. Alternatively, issue a software reset or cycle the power to reload the user-
programmable NVM bits.
8.3.3.3 NVM_CRC_ALARM_INTERNAL Bit
A logic 1 on NVM_CRC_ALARM_INTERNAL bit indicates that the internal NVM data is corrupt. During this
condition, all registers in the DAC are initialized with factory reset values, and any DAC registers can be written
to or read from. To reset the alarm bits to 0, issue a software reset (see the Software Reset section) command or
cycle power to the DAC.
8.3.4 Programmable Slew Rate
When the DAC data registers are written, the voltage on DAC output (VOUT) immediately transitions to the new
code following the slew rate and settling time specified in the Electrical Characteristics table. The slew rate
control feature allows the user to control the rate at which the output voltage (VOUT) changes. When this feature
is enabled (using SLEW_RATE[3:0] bits), the DAC output changes from the current code to the code in
MARGIN_HIGH (address 25h) or MARGIN_LOW (address 26h) registers (when margin high or low commands
are issued to the DAC) using the step and rate set in CODE_STEP and SLEW_RATE bits. With the default slew
rate control setting (CODE_STEP and SLEW_RATE bits, address D1h), the output changes smoothly at a rate
limited by the output drive circuitry and the attached load. Using this feature, the output steps digitally at a rate
defined by bits CODE_STEP and SLEW_RATE on address D1h. SLEW_RATE defines the rate at which the
digital slew updates; CODE_STEP defines the amount by which the output value changes at each update.
Table 2 and Table 3 show different settings for CODE_STEP and SLEW_RATE.
When the slew rate control feature is used, the output changes happen at the programmed slew rate. This
configuration results in a staircase formation at the output. Do not write to CODE_STEP, SLEW_RATE, or
DAC_DATA during the output slew.
Table 2. Code Step
REGISTER ADDRESS
AND NAME
CODE_STEP[2]
CODE_STEP[1]
CODE_STEP[0]
COMMENT
D1h, GENERAL_CONFIG
0
0
0
Code step size = 1 LSB
(default)
0
0
1
Code step size = 2 LSB
0
1
0
Code step size = 3 LSB
0
1
1
Code step size = 4 LSB
1
0
0
Code step size = 6 LSB
1
0
1
Code step size = 8 LSB
1
1
0
Code step size = 16 LSB
1
1
1
Code step size = 32 LSB


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