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DLPC900 Datasheet(PDF) 13 Page - Texas Instruments

No. de Pieza. DLPC900
Descripción  DLPC900 Digital Controller for Advanced Light Control
Descarga  83 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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DLPC900 Datasheet(HTML) 13 Page - Texas Instruments

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DLPC900
www.ti.com
DLPS037D – OCTOBER 2014 – REVISED MARCH 2019
Product Folder Links: DLPC900
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Port 1 and Port 2 Channel Data and Control Pin Functions (continued)
PIN (1) (2) (3)
I/O
POWER
I/O TYPE
(4)
CLK SYSTEM
DESCRIPTION
NAME
NUMBER
P1_HSYNC
AD21
VDD33
B2
D
P_CLK1,
P_CLK2, or
P_CLK3
Port 1 horizontal sync. While intended to be associated with
port 1, it can be programmed for use with port 2.
P2_A9
P2_A8
P2_A7
P2_A6
P2_A5
P2_A4
P2_A3
P2_A2
P2_A1 (5)
P2_A0 (5)
AD26
AD25
AB21
AC22
AD23
AB20
AC21
AD22
AE23
AB19
VDD33
I4
D
P_CLK1,
P_CLK2, or
P_CLK3
Port 2 A channel input pixel data (bit weight 128)
Port 2 A channel input pixel data (bit weight 64)
Port 2 A channel input pixel data (bit weight 32)
Port 2 A channel input pixel data (bit weight 16)
Port 2 A channel input pixel data (bit weight 8)
Port 2 A channel input pixel data (bit weight 4)
Port 2 A channel input pixel data (bit weight 2)
Port 2 A channel input pixel data (bit weight 1)
Unused, tie to 0
Unused, tie to 0
P2_B9
P2_B8
P2_B7
P2_B6
P2_B5
P2_B4
P2_B3
P2_B2
P2_B1 (5)
P2_B0 (5)
Y22
AB26
AA23
AB25
AA22
AB24
AC26
AB23
AC25
AC24
VDD33
I4
D
P_CLK1,
P_CLK2, or
P_CLK3
Port 2 B channel input pixel data (bit weight 128)
Port 2 B channel input pixel data (bit weight 64)
Port 2 B channel input pixel data (bit weight 32)
Port 2 B channel input pixel data (bit weight 16)
Port 2 B channel input pixel data (bit weight 8)
Port 2 B channel input pixel data (bit weight 4)
Port 2 B channel input pixel data (bit weight 2)
Port 2 B channel input pixel data (bit weight 1)
Unused, tie to 0
Unused, tie to 0
P2_C9
P2_C8
P2_C7
P2_C6
P2_C5
P2_C4
P2_C3
P2_C2
P2_C1 (5)
P2_C0 (5)
W23
V22
Y26
Y25
Y24
Y23
W22
AA26
AA25
AA24
VDD33
I4
D
P_CLK1,
P_CLK2, or
P_CLK3
Port 2 C channel input pixel data (bit weight 128)
Port 2 C channel input pixel data (bit weight 64)
Port 2 C channel input pixel data (bit weight 32)
Port 2 C channel input pixel data (bit weight 16)
Port 2 C channel input pixel data (bit weight 8)
Port 2 C channel input pixel data (bit weight 4)
Port 2 C channel input pixel data (bit weight 2)
Port 2 C channel input pixel data (bit weight 1)
Unused, tie to 0
Unused, tie to 0
P2_VSYNC
U22
VDD33
B2
D
P_CLK1,
P_CLK2, or
P_CLK3
Port 2 vertical sync. While intended to be associated with
port 2, it can be programmed for use with port 1.
P2_HSYNC
W26
VDD33
B2
D
P_CLK1,
P_CLK2, or
P_CLK3
Port 2 horizontal sync. While intended to be associated with
port 2, it can be programmed for use with port 1.


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