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MC10EPT20 Datasheet(Hoja de datos) 1 Page - ON Semiconductor

No. de Pieza. MC10EPT20
Descripción  LVTTL/LVCMOS to Differential LVPECL Translator
Descarga  4 Pages
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Fabricante  ONSEMI [ON Semiconductor]
Página de inicio  http://www.onsemi.com
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© Semiconductor Components Industries, LLC, 1999
September, 1999 – Rev. 1.0
1
Publication Order Number:
MC10EPT20/D
MC10EPT20
LVTTL/LVCMOS to
Differential LVPECL Translator
The MC10EPT20 is a LVTTL/LVCMOS to differential LVPECL
translator. Because LVPECL (Positive ECL) levels are used only
+3.3V and ground are required. The small outline 8–lead SOIC
package and the single gate of the EPT20 makes it ideal for those
applications where space, performance, and low power are at a
premium.
390ps Typical Propagation Delay
High Bandwidth to 1.0 GHz Typical
Differential LVPECL Outputs
Small Outline SOIC Package
PNP LVTTL Inputs for Minimal Loading
VCC Range of 3.0V to 3.6V
ESD Protection: >1.5KV HBM, >200V MM
Q Output will default HIGH with inputs open
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
Transistor Count = 150 devices
1
2
3
45
6
7
8
D
GND
VCC
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
Q
NC
Q
NC
NC
LVTTL
LVPECL
SO–8
D SUFFIX
CASE 751
PIN DESCRIPTION
PIN
Q, Q
D
LVTTL Input
FUNCTION
Differential LVPECL Outputs
http://onsemi.com
VCC
GND
Ground
Positive Supply
MARKING DIAGRAM
HPT20
Device
Package
Shipping
ORDERING INFORMATION
MC10EPT20D
SOIC
98 Units/Rail
MC10EPT20DR2
SOIC
2500 Tape & Reel
ALYW
1
8
1
8
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D




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