1.2 Data Memory Organization
Data memory is composed of Special Function Registers and General Purpose Registers.
The General Purpose Registers are accessed either directly or indirectly through the FSR register.
The Special Function Registers are registers used by the CPU and peripheral functions to control the
operation of the device.
In TLC157, the data memory is partitioned into four banks. Switching between these banks requires the RP1
and RP0 bits in the FSR register to be configured for the desired bank.
TABLE 1.1: Operational Registers Map
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
N/A (w)
OPTION
-
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
N/A (w)
IOSTA
Port A I/O Control Register
N/A (w)
IOSTB
Port B I/O Control Register
N/A (w)
IOSTC
Port C I/O Control Register
00h (r/w)
INDF
Uses contents of FSR to address data memory (not a physical register)
01h (r/w)
TMR0
8-bit real-time clock/counter
02h (r/w)
PCL
Low order 8 bits of PC
03h (r/w)
STATUS
GP2
GP1
GP0
TO
PD
Z
DC
C
04h (r/w)
FSR
RP1
(3)
RP0
(3)
Indirect data memory address pointer
05h (r/w)
PORTA
-
-
-
-
IOA3
IOA2
IOA1
IOA0
06h (r/w)
PORTB
IOB7
IOB6
IOB5
IOB4
IOB3
IOB2
IOB1
IOB0
07h (r/w)
PORTC
(1)
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
08h (r/w)
PCON
WDTE
EIS
LVDTE
ROC
-
-
-
-
09h (r/w)
WUCON
WUB7
WUB6
WUB5
WUB4
WUB3
WUB2
WUB1
WUB0
0Ah (r/w)
PCHBUF
(2)
-
-
-
-
-
Upper 3 bits Buffer of PC
0Bh (r/w)
PDCON
/PDB3
/PDB2
/PDB1
/PDB0
/PDA3
/PDA2
/PDA1
/PDA0
0Ch (r/w)
ODCON
ODB7
ODB6
ODB5
ODB4
ODB3
ODB2
ODB1
ODB0
0Dh (r/w)
PHCON
/PHB7
/PHB6
/PHB5
/PHB4
/PHB3
/PHB2
/PHB1
/PHB0
0Eh (r/w)
INTEN
GIE
-
-
-
-
INTIE
PBIE
T0IE
0Fh (r/w)
INTFLAG
-
-
-
-
-
INTIF
PBIF
T0IF
Legend: - = unimplemented, read as ‘0’,
Note 1 : PORTC is an 8-bit I/O Register for TLC155/157.
PORTC is a General Purpose Register for TLC154/156.
2 : There is only 1 bit in TLC154/155. There are only 2 bits in TLC156. And there are 3 bits in
TLC157.
3 : For TLC154/155/156, these bits are not used, read as ‘1’
TLC
TLC156
Rev0.95 Nov 20, 2003
P.2/TLC156