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GS71024U-12I Datasheet(PDF) 6 Page - GSI Technology

No. de pieza GS71024U-12I
Descripción Electrónicos  64K x 24 1.5Mb Asynchronous SRAM
Download  13 Pages
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Fabricante Electrónico  GSI [GSI Technology]
Página de inicio  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS71024U-12I Datasheet(HTML) 6 Page - GSI Technology

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GS71024T/U
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 11/2004
6/13
© 1999, GSI Technology
AC Characteristics
* These parameters are sampled and are not 100% tested
Read Cycle 1: CE = OE = VIL, WE = VIH
Read Cycle
Parameter
Symbol
-8
-9
-10
-12
-15
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Read cycle time
tRC
8—9—
10
12
15
ns
Address access time
tAA
—8—9—
10
12
15
ns
Chip enable access time (CE1, CE2)
tAC
—8—9—
10
12
15
ns
MUX control to output valid (V/S)
tAV
—8—9—
10
12
15
ns
Output enable to output valid (OE)
tOE
—4—
4.5
—5—6—7
ns
Output hold from address change
tOH
3—3—3—3—3—
ns
Output hold from MUX controls change
tOH1
3—3—3—3—3—
ns
Chip enable to output in low Z (CE1, CE2)
tLZ*
3—3—3—3—3—
ns
Output enable to output in low Z (OE)
tOLZ*
0—0—0—0—0—
ns
Chip disable to output in High Z (CE1, CE2)
tHZ*
—4—
4.5
—5—6—7
ns
Output disable to output in High Z (OE)
tOHZ*
—4—
4.5
—5—6—7
ns
tAA
tOH
tRC
Address
Data Out
Previous Data
Data valid
tOH1
tAV
V/S


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