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MC14515BDW Datasheet(PDF) 1 Page - ON Semiconductor

No. de pieza MC14515BDW
Descripción Electrónicos  4-Bit Transparent Latch/4-to-16 Line Decoder
Download  12 Pages
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Fabricante Electrónico  ONSEMI [ON Semiconductor]
Página de inicio  http://www.onsemi.com
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MC14515BDW Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14514B/D
MC14514B, MC14515B
4-Bit Transparent
Latch/4-to-16 Line Decoder
The MC14514B and MC14515B are two output options of a 4 to 16
line decoder with latched inputs. The MC14514B (output active high
option) presents a logical “1” at the selected output, whereas the
MC14515B (output active low option) presents a logical “0” at the
selected output. The latches are R–S type flip–flops which hold the
last input data presented prior to the strobe transition from “1” to “0”.
These high and low options of a 4–bit latch/4 to 16 line decoder are
constructed with N–channel and P–channel enhancement mode
devices in a single monolithic structure. The latches are R–S type
flip–flops and data is admitted upon a signal incident at the strobe
input, decoded, and presented at the output.
These complementary circuits find primary use in decoding
applications where low power dissipation and/or high noise immunity
is desired.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
– 0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 2.)
500
mW
TA
Ambient Temperature Range
– 55 to +125
°C
Tstg
Storage Temperature Range
– 65 to +150
°C
TL
Lead Temperature
(8–Second Soldering)
260
°C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
XX
= Specific Device Code
A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14514BCP
PDIP–24
15/Rail
MC14514BDW
SOIC–24
30/Rail
MC14514BDWR2
SOIC–24
1000/Tape & Reel
MARKING
DIAGRAMS
1
24
PDIP–24
P SUFFIX
CASE 709
MC145XXBCP
AWLYYWW
1
24
SOIC–24
DW SUFFIX
CASE 751E
145XXB
AWLYYWW
MC14515BCP
PDIP–24
15/Rail
MC14515BDW
SOIC–24
30/Rail
MC14515BDWR2
SOIC–24
1000/Tape & Reel


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