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TLC3544 Datasheet(PDF) 21 Page - Texas Instruments |
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TLC3544 Datasheet(HTML) 21 Page - Texas Instruments |
21 / 40 page TLC3544, TLC3548 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS SLAS266C – OCTOBER 2000 – REVISED MAY 2003 21 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 conversion mode (continued) Sweep Mode (Mode 10): During each operation, all of the channels listed in the sweep sequence (D[4:3] of the CFR register) are sampled and converted at one time according to the programmed sequence. The results are stored in the FIFO. When the FIFO threshold is reached, an interrupt (INT) is generated, and the operation ends. If the FIFO threshold is reached before all of the listed channels are visited, the remaining channels are ignored. This allows the host to change the sweep sequence length. The mode 10 operation starts with the WRITE CFR command to set the sweep sequence. The following triggers (CS, FS, or CSTART, depending on the interface) start the samplings and conversions of the listed channels in sequence until the FIFO threshold is hit. If CS or FS starts the sampling, the SDI data must be any one of the SELECT commands to set the converter in the conversion state. However, this command is a dummy code. It does not change the existing conversion sequence. After the FIFO is full, the converter waits for the FIFO READ. It does nothing before the FIFO READ or the WRITE CFR command is issued. The host must read the FIFO completely or write the CFR. If CSTART triggers the samplings, the host must issue an extra SELECT/CONVERSION command (select any channel) via CS or FS after the FIFO READ or WRITE CFR. This extra period is named the arm period and is used to set the converter into the conversion state, but does not affect the existing conversion sequence. Besides, if FS initiates the operation and CSTART triggers the sampling and conversions, CS must not toggle during the conversion. Repeat Sweep Mode (Mode 11): This mode works in the same way as mode 10, except that it is not necessary to read the FIFO before the next operation after the FIFO threshold is hit. The next SWEEP can repeat immediately, but the contents in the FIFO are replaced by the new results. The host can read the FIFO completely, then issue the next SWEEP or repeat the SWEEP immediately (with the existing sweep sequence) by issuing sampling/conversion triggers (CS, FS or CSTART) or change the device setting with the WRITE CFR. The memory effect of charge redistribution DAC exists when the mux switches from one channel to another. This degrades the channel-to-channel isolation if the channel changes after each conversion. For example, in mode 10 and 11, the isolation is about 70 dB for the sweep sequence 0-1-2-3-4 (refer to Figure 8). The memory effect can be reduced by increasing the sampling time or using the sweep sequence 0-0-2-2-4-4-6-6 and ignoring the first sample of each channel. Figure 8 shows the typical isolation vs throughput rate when applying a sine signal (35 kHz, 3.5 Vp-p) on CH0 and dc on CH1 converting both channels alternately and measuring the attenuation of the sine wave in CH1. Throughput – KSPS 60 70 80 90 100 0 50 100 150 200 CHANNEL-TO-CHANNEL ISOLATION vs THROUGHPUT Figure 8 |
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