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MSP430F5507 Datasheet(PDF) 24 Page - Texas Instruments |
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MSP430F5507 Datasheet(HTML) 24 Page - Texas Instruments |
24 / 125 page 24 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Specifications Copyright © 2009–2020, Texas Instruments Incorporated (1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN). (2) Also applies to the RST pin when its pullup or pullup resistor is enabled. 5.7 Schmitt-Trigger Inputs – General-Purpose I/O (1) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VIT+ Positive-going input threshold voltage 1.8 V 0.80 1.40 V 3 V 1.50 2.10 VIT– Negative-going input threshold voltage 1.8 V 0.45 1.00 V 3 V 0.75 1.65 Vhys Input voltage hysteresis (VIT+ – VIT–) 1.8 V 0.3 0.85 V 3 V 0.4 1.0 RPull Pullup or pulldown resistor(2) For pullup: VIN = VSS For pulldown: VIN = VCC 20 35 50 k Ω CI Input capacitance VIN = VSS or VCC 5 pF (1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions. (2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int). 5.8 Inputs – Ports P1 and P2 (1) (P1.0 to P1.7, P2.0 to P2.7) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT t(int) External interrupt timing(2) Port P1, P2: P1.x to P2.x, External trigger pulse duration to set interrupt flag 2.2 V, 3 V 20 ns (1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted. (2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled. 5.9 Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT Ilkg(Px.y) High-impedance leakage current (1) (2) 1.8 V, 3 V ±50 nA (1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified. (2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified. 5.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT VOH High-level output voltage I(OHmax) = –3 mA (1) 1.8 V VCC – 0.25 VCC V I(OHmax) = –10 mA (2) VCC – 0.60 VCC I(OHmax) = –5 mA (1) 3 V VCC – 0.25 VCC I(OHmax) = –15 mA (2) VCC – 0.60 VCC VOL Low-level output voltage I(OLmax) = 3 mA (1) 1.8 V VSS VSS + 0.25 V I(OLmax) = 10 mA (2) VSS VSS + 0.60 I(OLmax) = 5 mA (1) 3 V VSS VSS + 0.25 I(OLmax) = 15 mA (2) VSS VSS + 0.60 |
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