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MSP430F5507 Datasheet(PDF) 56 Page - Texas Instruments |
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MSP430F5507 Datasheet(HTML) 56 Page - Texas Instruments |
56 / 125 page 56 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 SLAS645L – JULY 2009 – REVISED MAY 2020 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Detailed Description Copyright © 2009–2020, Texas Instruments Incorporated Table 6-7. Port Mapping Mnemonics and Functions (continued) VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION (1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are ignored, which results in a read value of 31. 11 PM_UCA1RXD USCI_A1 UART RXD (Direction controlled by USCI – input) PM_UCA1SOMI USCI_A1 SPI slave out master in (direction controlled by USCI) 12 PM_UCA1TXD USCI_A1 UART TXD (Direction controlled by USCI – output) PM_UCA1SIMO USCI_A1 SPI slave in master out (direction controlled by USCI) 13 PM_UCA1CLK USCI_A1 clock input/output (direction controlled by USCI) PM_UCB1STE USCI_B1 SPI slave transmit enable (direction controlled by USCI) 14 PM_UCB1SOMI USCI_B1 SPI slave out master in (direction controlled by USCI) PM_UCB1SCL USCI_B1 I2C clock (open drain and direction controlled by USCI) 15 PM_UCB1SIMO USCI_B1 SPI slave in master out (direction controlled by USCI) PM_UCB1SDA USCI_B1 I2C data (open drain and direction controlled by USCI) 16 PM_UCB1CLK USCI_B1 clock input/output (direction controlled by USCI) PM_UCA1STE USCI_A1 SPI slave transmit enable (direction controlled by USCI) 17 PM_CBOUT1 None Comparator_B output 18 PM_MCLK None MCLK 19 PM_RTCCLK None RTCCLK output 20 PM_UCA0RXD USCI_A0 UART RXD (Direction controlled by USCI – input) PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI) 21 PM_UCA0TXD USCI_A0 UART TXD (Direction controlled by USCI – output) PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI) 22 PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI) PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI) 23 PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI) PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI) 24 PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI) PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI) 25 PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI) PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI) 26–30 Reserved None DVSS 31 (0FFh)(1) PM_ANALOG Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals. Table 6-8. Default Mapping PIN PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION P4.0/P4MAP0 PM_UCB1STE/PM_UCA1CLK USCI_B1 SPI slave transmit enable (direction controlled by USCI) USCI_A1 clock input/output (direction controlled by USCI) P4.1/P4MAP1 PM_UCB1SIMO/PM_UCB1SDA USCI_B1 SPI slave in master out (direction controlled by USCI) USCI_B1 I2C data (open drain and direction controlled by USCI) P4.2/P4MAP2 PM_UCB1SOMI/PM_UCB1SCL USCI_B1 SPI slave out master in (direction controlled by USCI) USCI_B1 I2C clock (open drain and direction controlled by USCI) P4.3/P4MAP3 PM_UCB1CLK/PM_UCA1STE USCI_A1 SPI slave transmit enable (direction controlled by USCI) USCI_B1 clock input/output (direction controlled by USCI) P4.4/P4MAP4 PM_UCA1TXD/PM_UCA1SIMO USCI_A1 UART TXD (Direction controlled by USCI – output) USCI_A1 SPI slave in master out (direction controlled by USCI) P4.5/P4MAP5 PM_UCA1RXD/PM_UCA1SOMI USCI_A1 UART RXD (Direction controlled by USCI – input) USCI_A1 SPI slave out master in (direction controlled by USCI) P4.6/P4MAP6 PM_NONE None DVSS P4.7/P4MAP7 PM_NONE None DVSS |
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