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ADD8502 Datasheet(PDF) 5 Page - Analog Devices |
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ADD8502 Datasheet(HTML) 5 Page - Analog Devices |
5 / 16 page REV. 0 ADD8502 –5– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Name I/O Description 1VL Logic Select Pin I Logic Supply Voltage. Connect to supply used for system logic. Can accept 2.7 V to VDD. 2DIN Serial Data Input I When CS is LOW, the input on this pin is shifted into the internal shift register on the rising edge of SCK. 3 SCK Serial Clock I Accepts up to 10 MHz input. The rising edge on this clock will shift the data on DIN Pin into the internal shift registers. 4 CS-LD Load I When CS-LD is LOW, SCK is enabled for shifting data on the D IN input into the internal shift register on the rising edge of SCK. Data is loaded MSB first. 5CMLogic Control 2 I When CM is LOW, COM will output the voltage level input on COM_M. for VCOM When CM is HIGH, COM levels will be determined by the input on REV1. 6 CV4 Logic Control V4 I If CV4 is HIGH, V4 output is the output of the op amp A4. If CV4 is LOW, V4 is connected to COM and op amp A4 is shut down. Refer to Table II. 7 REV1 Logic Control 1 I With CM HIGH, a HIGH on REV1 will cause COM to output the voltage level for VCOM input at VDD. A LOW on REV1 will cause COM to output the voltage level input at GND. 8NCNo Connect Unused Pin 9NCNo Connect Unused Pin 10 COM Common Output O If CM is LOW, COM will output the voltage input at COM_M. If CM is HIGH, COM will output the voltage input at VDD when REV1 is HIGH and will output the voltage input at GND when REV1 is LOW. Refer to Table II. 11 COM_M Common System I COM_M is a system voltage reference input between 2.5 V and 3.5 V. This may VREF be the system 3.3 V supply. 12 NC No Connect Unused Pin 13 GND Ground I Ground. Nominally 0 V. 14 V4 Output O Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF). When PSK is LOW, these outputs will be Hi-Z. 15 V3 Output O Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF). When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z. 16 V2 Output O Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF). When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z. 17 V1 Output O Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF). When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z. 18 V0 Output O Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF). When PSK is LOW, these outputs will be Hi-Z. 19 VDD Supply I Supply Voltage. Nominally 5 V. 20 NC No Connect Unused Pin PIN CONFIGURATION V0 V1 V2 V3 V4 GND 18 17 16 15 14 13 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) 24 VL DIN SCK CS-LD CM CV4 NC = NO CONNECT ADD8502 23 22 21 20 19 78 9 10 11 12 1 2 3 4 5 6 |
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