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ISD94100 Datasheet(PDF) 46 Page - Nuvoton Technology Corporation |
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ISD94100 Datasheet(HTML) 46 Page - Nuvoton Technology Corporation |
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46 / 109 page  ISD94100 Series Datasheet Sep 09, 2019 Page 46 of 109 Rev1.13 42 26 PWM0_P1_INT PWM0 pair 1 interrupt 43 27 PWM0_P2_INT PWM0 pair 2 interrupt 44 ~ 47 28 ~ 31 Reserved Reserved 48 32 TMR0_INT Timer 0 interrupt 49 33 TMR1_INT Timer 1 interrupt 50 34 TMR2_INT Timer 2 interrupt 51 35 TMR3_INT Timer 3 interrupt 52 36 UART0_INT UART0 interrupt 53 37 Reserved Reserved 54 38 I2C0_INT I2C0 interrupt 55 39 I2C1_INT I2C1 interrupt 56 40 PDMA_INT PDMA interrupt 57 41 Reserved Reserved 58 42 EADC0_INT EADC interrupt source 0 59 43 EADC1_INT EADC interrupt source 1 60 44 Reserved Reserved 61 45 Reserved Reserved 62 46 EADC2_INT EADC interrupt source 2 63 47 EADC3_INT EADC interrupt source 3 64 ~ 66 48~ 50 Reserved Reserved 67 51 SPI2_INT SPI2 interrupt 68 52 DMIC_INT DMIC interrupt 69 53 USBD_INT USB device interrupt 70 ~ 71 54 ~ 55 Reserved Reserved 72 56 VAD_INT VAD interrupt 73 ~ 77 57 ~ 61 Reserved Reserved 78 62 DPWM_INT DPWM interrupt 79 ~ 83 63 ~ 67 Reserved Reserved 84 68 I2S0_INT I2S0 interrupt 85 ~ 111 69 ~ 95 Reserved Reserved Table 6.2.7-2 Interrupt Number Table 6.2.7.2 Operation Description NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state |
Número de pieza similar - ISD94100 |
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Descripción similar - ISD94100 |
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