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JN5189 Datasheet(PDF) 37 Page - NXP Semiconductors |
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JN5189 Datasheet(HTML) 37 Page - NXP Semiconductors |
37 / 92 page JN5189 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1.2 — June 2020 37 of 92 NXP Semiconductors IEEE 802.15.4 low power wireless MCU JN5189(T)/JN5188(T) • Special operating mode allows operation at up to 9600 baud using the 32 kHz RTC oscillator as the USART clock. This mode can be used, with USART0, while the device is in Power-down mode and can wake-up the device when a character is received 8.12 Serial Peripheral Interfaces-bus (SPI-bus) The SPI-bus allows high-speed synchronous data transfer between the JN5189 and peripheral devices. Two SPI-buses are supported which can independently operate as a master or slave to support a range of system configurations. • 2 SPI-bus interfaces: SPI0 and SPI1 can be both configured as master or slave interfaces • Data transmits of 1 to 16 bits supported directly. Larger frames supported by software • The SPI-bus function supports separate transmit and receive FIFOs with 4 16-bit entries each • Support DMA transfers: SPIn transmit and receive functions can operate with the system DMA controller • Data can be transmitted to a slave without the need to read incoming data. This can be useful while setting up an SPI-bus memory • Up to 3 slave select input/outputs with selectable polarity and flexible usage Remark: Texas Instruments SSI and National Microwire modes are not supported. 8.13 I2C-bus interfaces The JN5189 supports the industry standard I2C-bus, a 2-wire synchronous serial interface that can operate as a master or slave, providing a simple and efficient method of data exchange between devices. The system uses serial data and clock to perform bidirectional data transfers. • 2 I2C-bus interfaces, one with I2C compliant IO cells • Independent master, slave and monitor functions • Bus speeds supported: – Standard mode, up to 100 kbits/s – Fast-mode, up to 400 kbits/s – Fast-mode Plus, up to 1 Mbits/s (on specific I2C-bus pins) – High speed mode, 3.4 Mbits/s as a slave only (on specific I2C-bus pins) • Supports both multi-master and multi-master with slave functions • Multiple I2C-bus slave addresses supported in hardware • One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple I2C-bus addresses • 10-bit addressing supported with software assist • Supports System Management Bus (SMBus) • Separate DMA requests for master, slave, and monitor functions • No chip clocks are required in order to receive and compare an address as a slave, so this event can wake up the device from Power-down mode with I2C0 |
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