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DRV8714-Q1 Datasheet(PDF) 33 Page - Texas Instruments

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No. de pieza DRV8714-Q1
Descripción Electrónicos  DRV871x-Q1 Automotive Multi-Channel Smart Half-Bridge Gate Drivers With Wide Common Mode Current Sense Amplifiers
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Table 8-15. Smart Gate Driver Terminology Descriptions (continued)
Core Function
Terminology
Description
PDR
(Pre-charge)
ICHR_INIT
Gate drive source current initial value for charge control loop. Configured with the
PRE_CHR_INIT_xx control register
IPRE_CHR
Gate drive source current for pre-charge period after control loop lock. Adjustment rate configured
with the KP_PDR_x control register. Max current clamp configured with the PRE_MAX_x control
register.
tPRE_CHR
Gate drive source current pre-charge period duration. Configured with the T_PRE_CHR_x control
register.
tDON
Delay time from start of pre-charge period to rising VSH crossing VSH_L threshold. Configure with
T_DON_DOFF_x control register.
IDCHR_INIT
Gate drive sink current initial value for discharge period control loop. Configured with the
PRE_DCHR_INIT_x control register.
IPRE_DCHR
Gate drive sink current for pre-discharge period after control loop lock. Adjustment rate configured
with the KP_PDR_x control register. Max current clamp configured with the PRE_MAX_x control
register.
tPRE_DCHR
Gate drive sink current pre-discharge period duration. Configured with the T_PRE_DCHR_x control
register.
tDOFF
Delay time from start of pre-discharge period to falling VSH crossing VSH_H threshold. Configure
with T_DON_DOFF_x control register.
VSH_L
Low voltage threshold for VSH switch-node. Configured with the AGD_THR control register.
VSH_H
High voltage threshold for VSH switch-node. Configured with the AGD_THR control register.
PDR
(Post-charge)
IPST_CHR
Gate drive source current for post-charge period. Adjustment rate configured with the KP_PST_x
control register.
tPST_CHR
Gate drive source current post-charge period duration.
IPST_DCHR
Gate drive sink current for post-discharge period. Adjustment rate configured with the KP_PST_x
control register.
tPST_DCHR
Gate drive source current post-charge period duration.
IFW_CHR
Freewheeling charge current. Configured with the FW_MAX_x control register.
IFW_DCHR
Freewheeling discharge current. Configured with the FW_MAX_x control register.
STC
tRISE
Time duration for VSHx to cross from VSHx_L to VSHx_H threshold.
tFALL
Time duration for VSHx to cross from VSHx_H to VSHx_L threshold.
8.3.4.1 Functional Block Diagram
Figure 8-11 shows a high level function block diagram for the half-bridge gate driver architecture. The gate driver
blocks provide a variety of functions for MOSFET control, feedback, and protection. This includes
complimentary, push-pull high-side and low-side gate drivers with adjustable drive currents, control logic level
shifters, VDS, VGS, and VSH (switch-node) feedback comparators, a high-side Zener clamp, plus passive and
active pulldown resistors.
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DRV8714-Q1, DRV8718-Q1
SLVSEA2 – AUGUST 2020
Copyright © 2020 Texas Instruments Incorporated
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