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UPD70F3208 Datasheet(PDF) 22 Page - NEC

No. de pieza UPD70F3208
Descripción Electrónicos  32-Bit Single-Chip Microcontrollers
Download  757 Pages
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Fabricante Electrónico  NEC [NEC]
Página de inicio  http://www.nec.com/
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UPD70F3208 Datasheet(HTML) 22 Page - NEC

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User’s Manual U15862EJ3V0UD
22
LIST OF FIGURES (4/6)
Figure No.
Title
Page
12-1
Block Diagram of Watchdog Timer 1..........................................................................................................409
12-2
Block Diagram of Watchdog Timer 2..........................................................................................................416
13-1
Block Diagram of A/D Converter ................................................................................................................420
13-2
Operation Sequence ..................................................................................................................................424
13-3
Relationship Between Analog Input Voltages and A/D Conversion Results...............................................427
13-4
Power Fail Monitoring Function (PFCM = 0) ..............................................................................................429
13-5
Timing of A/D Converter Sampling and A/D Conversion Start Delay .........................................................430
13-6
Overall Error...............................................................................................................................................432
13-7
Quantization Error ......................................................................................................................................433
13-8
Zero-Scale Error.........................................................................................................................................433
13-9
Full-Scale Error ..........................................................................................................................................434
13-10
Differential Linearity Error...........................................................................................................................434
13-11
Integral Linearity Error................................................................................................................................435
13-12
Sampling Time ...........................................................................................................................................435
14-1
Block Diagram of D/A Converter ................................................................................................................436
15-1
Selecting Mode of UART2 or I
2C1 ..............................................................................................................441
15-2
Block Diagram of Asynchronous Serial Interface n ....................................................................................444
15-3
Format of Asynchronous Serial Interface Transmit/Receive Data ..............................................................453
15-4
Asynchronous Serial Interface Transmission Completion Interrupt Timing ................................................455
15-5
Continuous Transmission Processing Flow................................................................................................457
15-6
Continuous Transmission Starting Procedure ............................................................................................458
15-7
Continuous Transmission End Procedure ..................................................................................................459
15-8
Asynchronous Serial Interface Reception Completion Interrupt Timing .....................................................461
15-9
When Reception Error Interrupt Is Separated from INTSRn Interrupt (ISRMn Bit = 0)...............................462
15-10
When Reception Error Interrupt Is Included in INTSRn Interrupt (ISRMn Bit = 1) ......................................462
15-11
Noise Filter Circuit ......................................................................................................................................464
15-12
Timing of RXDn Signal Judged as Noise ...................................................................................................464
15-13
Configuration of Baud Rate Generator n (BRGn).......................................................................................465
15-14
Allowable Baud Rate Range During Reception..........................................................................................470
15-15
Transfer Rate During Continuous Transmission ........................................................................................472
16-1
Block Diagram of Clocked Serial Interface .................................................................................................476
16-2
Timing Chart in Single Transfer Mode........................................................................................................486
16-3
Timing Chart According to Clock Phase Selection .....................................................................................488
16-4
Timing Chart of Interrupt Request Signal Output in Delay Mode................................................................490
16-5
Repeat Transfer (Receive-Only) Timing Chart ...........................................................................................493
16-6
Repeat Transfer (Transmission/Reception) Timing Chart ..........................................................................495
16-7
Timing Chart of Next Transfer Reservation Period.....................................................................................496
16-8
Transfer Request Clear and Register Access Conflict ...............................................................................498
16-9
Interrupt Request and Register Access Conflict.........................................................................................499


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