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FIN12ACMLX Datasheet(PDF) 9 Page - Fairchild Semiconductor |
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FIN12ACMLX Datasheet(HTML) 9 Page - Fairchild Semiconductor |
9 / 21 page Preliminary 9 www.fairchildsemi.com Application Mode Diagrams Modes 1, 2, 3: Unidirectional Data Transfer FIGURE 8. Simplified Block Diagram for Unidirectional Serializer and Deserializer Figure shows the basic operation diagram when a pair of SerDes is configured in an unidirectional operation mode. Master Operation: The device will... (Please refer to Figure ) 1. During power-up the device will be configured as a serializer based on the value of the DIRI signal. 2. Accept CKREF_M word clock and generate a bit clock with embedded word boundary. This bit clock will be sent to the slave device through the CKSO port. 3. Receive parallel data on the rising edge of STROBE_M. 4. Generate and transmit serialized data on the DS sig- nals which is source synchronous with CKSO. 5. Generate an embedded word clock for each strobe sig- nal. Slave Operation: The device will... 1. Be configured as a deserializer at power-up based on the value of the DIRI signal. 2. Accept an embedded word boundary bit clock on CKSI. 3. Deserialize the DS Data stream using the CKSI input clock. 4. Write parallel data onto the DP_S port and generate the CKP_S. CKP_S will only be generated when a valid data word occurs. FIGURE 9. Unidirectional Serializer and Deserializer |
Número de pieza similar - FIN12ACMLX |
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Descripción similar - FIN12ACMLX |
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