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UPD70F3114 Datasheet(PDF) 80 Page - NEC |
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UPD70F3114 Datasheet(HTML) 80 Page - NEC |
80 / 692 page 80 User’s Manual U15195EJ5V0UD CHAPTER 4 BUS CONTROL FUNCTION The V850E/IA2 is provided with an external bus interface function by which external I/O and memories, such as ROM and RAM, can be connected. 4.1 Features • 16-bit/8-bit data bus sizing function • Wait function • Programmable wait function: up to 7 wait states can be inserted • External wait function via WAIT pin • Idle state insertion function • External device connection enabled via bus control/port alternate function pins 4.2 Bus Control Pins The following pins are used for connection to external devices. Bus Control Pin (Function When in Control Mode) Function When in Port Mode Register for Port/Control Mode Switching Address/data bus (AD0 to AD15) PDL0 to PDL15 (port DL) PMCDL Address bus (A16 to A21) PDH0 to PDH5 (port DH) PMCDH Read/write control (LWR/UWR, RD, ASTB) PCT0, PCT1, PCT4, PCT6 (port CT) PMCCT External wait control (WAIT) PCM0 (port CM) Internal system clock (CLKOUT) PCM1 (port CM) PMCCM Remark In the case of ROMless mode, when the system is reset, each bus control pin becomes valid unconditionally. 4.2.1 Pin status during internal ROM, internal RAM, and on-chip peripheral I/O access When the internal ROM and RAM are accessed, both the address bus and address/data bus become undefined. The external bus control signal becomes inactive. When on-chip peripheral I/O are accessed, both the address bus and address/data bus output the address of the on-chip peripheral I/O currently being accessed. No data is output. The external bus control signal becomes inactive. |
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