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UPD70F3116 Datasheet(PDF) 51 Page - NEC |
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UPD70F3116 Datasheet(HTML) 51 Page - NEC |
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51 / 826 page  CHAPTER 3 CPU FUNCTION 51 User’s Manual U14492EJ5V0UD 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. To read/write these system registers, specify a system register number indicated below using the system register load/store instruction (LDSR or STSR instruction). Table 3-2. System Register Numbers Operand Specification No. System Register Name LDSR Instruction STSR Instruction 0 Status saving register during interrupt (EIPC) Note 1 1 Status saving register during interrupt (EIPSW) Note 1 2 Status saving register during NMI (FEPC) 3 Status saving register during NMI (FEPSW) 4 Interrupt source register (ECR) × 5 Program status word (PSW) 6 to 15 Reserved number for future function expansion (operations that access these register numbers cannot be guaranteed). × × 16 Status saving register during CALLT execution (CTPC) 17 Status saving register during CALLT execution (CTPSW) 18 Status saving register during exception/debug trap (DBPC) Note 2 Note 2 19 Status saving register during exception/debug trap (DBPSW) Note 2 Note 2 20 CALLT base pointer (CTBP) 21 to 31 Reserved number for future function expansion (operations that access these register numbers cannot be guaranteed). × × Notes 1. Because this register has only one set, to allow multiple interrupts, it is necessary to save this register by program. 2. These registers can be accessed only after DBTRAP instruction execution and before DBRETI instruction execution. Caution Even if bit 0 of EIPC, FEPC, or CTPC is set to 1 with the LDSR instruction, bit 0 will be ignored when the program is returned by the RETI instruction after interrupt servicing (because bit 0 of the PC is fixed to 0). When setting the value of EIPC, FEPC, or CTPC, use an even value (bit 0 = 0). Remark : Access allowed ×: Access prohibited |
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