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UPD703103A Datasheet(PDF) 42 Page - NEC

No. de Pieza. UPD703103A
Descripción  32-Bit Single-Chip Microcontrollers
Descarga  99 Pages
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Fabricante  NEC [NEC]
Página de inicio  http://www.nec.com/
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UPD703103A Datasheet(HTML) 42 Page - NEC

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CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
Application Note U17121EJ1V1AN
42
3.4.10 SDRAM_CTL register
After reset: 00070230H
R/W
Offset address: 48H
31
24 23
16 15
13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
CYCLE_LATENCY
0
0
0
0
0
0
0
0
0
Bit Name
R/W
Function
CYCLE_LATENCY
R/W
Sets the latency for successive main memory (SDRAM) accesses from the PCI device.
A latency of up to 7,650 ns can be set.
00H: No latency
01H: 1 PCI clock (30 ns)
:
FFH: 255 PCI clocks (7,650 ns)
BUS_SIZE
R/W
Sets the bit width of the data bus.
0: 16-bit width
1: 32-bit width
CAS_LATENCY
R/W
Sets the CAS latency.
00: Setting prohibited
01: 1
10: 2
11: 3
WAIT_STATE
R/W
Sets the wait interval of ACT
→ CMD, PRE → ACT, and CMD → ACT.
00: Setting prohibited
01: 1 clock
10: 2 clocks
11: 3 clocks
COLUMN_SIZE
R/W
Sets the bit width of the column address.
00: 8-bit width
01: 9-bit width
10: 10-bit width
11: 11-bit width


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