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UPD703103A Datasheet(PDF) 47 Page - NEC

No. de Pieza. UPD703103A
Descripción  32-Bit Single-Chip Microcontrollers
Descarga  99 Pages
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Fabricante  NEC [NEC]
Página de inicio  http://www.nec.com/
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UPD703103A Datasheet(HTML) 47 Page - NEC

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CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
Application Note U17121EJ1V1AN
47
3.8 Timing
The timing for each interface of the PCI host bridge macro is shown below.
3.8.1 External bus interface timing
CPU write/CPU read access is performed from the CPU using the bus interface (Figures 3-6 and 3-7).
When accessing SDRAM from the PCI host bridge macro, bus hold is performed and the main memory is
write/read accessed (Figures 3-8 to 3-10).
Figure 3-6. CPU Write Access
I_CPU_CSx_B
I_CPU_WE_B
I_CPU_WAIT_B
I_CPU_ADR0 to
I_CPU_ADR19
I_CPU_DATA0 to
I_CPU_DATA31
I_CPU_BE_B0 to
I_CPU_BE_B3
I_PCLK
Valid
Valid
1111
1111
0000
Remark
x = 0 to 2
Figure 3-7. CPU Read Access
I_PCLK
I_CPU_CSx_B
I_CPU_OE_B
I_CPU_WAIT_B
I_CPU_ADR0 to
I_CPU_ADR19
I_CPU_DATA0 to
I_CPU_DATA31
EN_CPU_DATA
I_CPU_BE_B0 to
I_CPU_BE_B3
1111
1111
0000
Valid
Valid
Remark
x = 0 to 2


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