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UPD703103A Datasheet(PDF) 50 Page - NEC

No. de Pieza. UPD703103A
Descripción  32-Bit Single-Chip Microcontrollers
Descarga  99 Pages
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Fabricante  NEC [NEC]
Página de inicio  http://www.nec.com/
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UPD703103A Datasheet(HTML) 50 Page - NEC

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CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
Application Note U17121EJ1V1AN
50
3.8.2 PCI bus interface timing
The PCI host bridge macro supports the following PCI bus interface timing.
(1) PCI bus master cycle timing
The timing of access from the CPU to the PCI device is shown below.
(a) Configuration read/write cycle, I/O read/write cycle, and memory read/write cycle
(i)
Read cycle
Timing type: Configuration register read, internal I/O register read, memory read
Figure 3-11. Read Cycle
AD
H
DEVSEL#
TRDY#
FRAME#
STOP#
IRDY#
PCICLK
(ii) Write cycle
Timing type: Configuration register write, internal I/O register write, memory write
Figure 3-12. Write Cycle
AD
H
DEVSEL#
TRDY#
FRAME#
STOP#
IRDY#
PCICLK


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