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UPD703103A Datasheet(PDF) 65 Page - NEC

No. de Pieza. UPD703103A
Descripción  32-Bit Single-Chip Microcontrollers
Descarga  99 Pages
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Fabricante  NEC [NEC]
Página de inicio  http://www.nec.com/
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UPD703103A Datasheet(HTML) 65 Page - NEC

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CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION
Application Note U17121EJ1V1AN
65
4.6 Cautions on Designing FPGA
Cautions when fitting an FPGA using Altera’s “Quartusll Design Software” are shown below.
4.6.1 FPGA fitting design
(1) Set the “I/O Standard” buffer type to “3.3-V PCI” for the following PCI bus interface pins.
Pin Name/Usage
Dir
I/O Standard
INTA
input
3.3-V PCI
INTB
input
3.3-V PCI
FRAME
bidir
3.3-V PCI
DEVSEL
bidir
3.3-V PCI
REQ1
input
3.3-V PCI
REQ2
input
3.3-V PCI
GNT1
output
3.3-V PCI
GNT2
output
3.3-V PCI
IRDY
bidir
3.3-V PCI
TRDY
bidir
3.3-V PCI
STOP
bidir
3.3-V PCI
PCIRST
output
3.3-V PCI
AD0 to AD31
bidir
3.3-V PCI
CBE0 to CBE3
bidir
3.3-V PCI
PAR
bidir
3.3-V PCI
PERR
bidir
3.3-V PCI
SERR
input
3.3-V PCI
(2) Determine the pin assignment taking equal length wiring into consideration for the PCI bus interface pins.
(3) Specify the “PCLK” and “SDCLK” signals as Global CLK.
4.6.2 PCI bus interface timing parameters (as constraint of PCI CLK = 33 MHz)
Adjust the timing so that the following PCI specification values are satisfied.
(1) Input setup time to CLK point to point
Pin
Setup
Hold
REQ1, REQ2
10 ns
0 ns
Other PCI pins
7 ns
0 ns


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